IP Library Granted Patent US 7,983,495
Granted Patent B2
US 7,983,495 · App. 11/889,772 · Granted Jul 19, 2011

Image processing device and method

Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 7,983,495
App. No.
11/889,772
Granted
Jul 19, 2011
Kind
B2
Abstract

An image processing device for use with a storage circuit processes image data for a frame formed by a plurality of pixels. The image processing device includes a first functional macro performing first image processing on the image data, generating first processed image data, and temporarily storing the first processed image in a predetermined region of the storage circuit. A second functional macro performs second image processing following the first image processing. The second functional macro reads the first processed image data from the predetermined region of the storage circuit, performs the second image processing on the first processed image data, and generates second processed image data. A monitor circuit, arranged in the first or second functional macro, monitors a frame processed by the other one of the functional macros and a number of a data line in the frame that is being processed.

Claims (37)

1. An image processing device comprising:

a circuit performing processing image data for a frame formed by a plurality of pixels with a storage circuit;

a first functional macro performing first image processing on the image data, generating first processed image data, and temporarily storing the first processed image in a predetermined region of the storage circuit;

a second functional macro performing second image processing following the first image processing, the second functional macro reading the first processed image data from the predetermined region of the storage circuit, performing the second image processing on the first processed image data, and generating second processed image data; and

a monitor circuit, arranged within at least one of the first and the second functional macros, monitoring a frame being processed by the other one of the functional macros and a number of a data line in the frame that is being processed.

2. The image processing device according to claim 1 , further comprising a setting circuit setting a successive frame processing number for each functional macro.

3. The image processing device according to claim 1 , wherein the first and second functional macros each include a direct memory access controller exchanging the image data with the storage circuit in a direct memory access format.

4. The image processing device according to claim 1 , wherein a mode is included for successively processing a plurality of frames, and the monitor circuit includes:

a first monitor circuit, arranged in the first functional macro, monitoring the frame being processed by the second functional macro and the number of the data line in the frame that is being processed; and

a second monitor circuit, arranged in the second functional macro, monitoring the frame being processed by the first functional macro and the number of the data line in the frame that is being processed, wherein the first monitor circuit and the second monitor circuit notify each other of a result of the monitoring.

5. The image processing device according to claim 4 , wherein each functional macro divides each of the plurality of frames into a plurality of blocks and processes each block, and each functional macro immediately starts the processing of the next frame without performing an interruption process when the processing of all of the blocks in the preceding frame ends.

6. The image processing device according to claim 1 , wherein the first functional macro overwrites the first processed image data of the preceding frame stored in the storage circuit with the first image processed image data of the next frame based on the number of the data line in the preceding frame that is being processed by the second functional macro.

7. The image processing device according to claim 1 , wherein the first functional macro specifies a storage region storing the image data read by the second functional macro from the image data processed by the first functional macro, and uses the specified storage region as a vacant region storing image data after image processing the next frame.

8. The image processing device according to claim 1 comprising:

a plurality of functional macros including the first and second functional macros, wherein final image data generated through sequential processing by the plurality of functional macros is transferred from the storage circuit to an external storage.

9. An image processing method comprising:

performing first image processing on image data for a frame formed by a plurality of pixels and generating first processed image data via a first functional macro of a processor;

temporarily storing the first processed image in a predetermined region of the storage circuit via the first functional macro;

reading the first processed image data from the predetermined region of the storage circuit via a second functional macro of the processor;

performing the second image processing on the read first processed image data and generating second processed image data by the second functional macro; and

monitoring, via a monitor circuit arranged within at least one of the first and second functional macros, a frame that is being processed by the other one of the at least one of the first and second functional macros and a number of a data line in the frame that is being processed.

10. The image processing method according to claim 9 , further comprising:

setting a successive frame processing number for each functional macro.

11. The image processing method according to claim 9 , further comprising:

exchanging the image data in a direct memory access format between the storage circuit and each of the first and second functional macros.

12. The image processing method according to claim 9 including a mode successively processing a plurality of frames, wherein the monitoring includes:

monitoring the frame being processed via the second functional macro and the number of the data line in the frame that is being processed with the first functional macro;

monitoring the frame being processed via the first functional macro and the number of the data line in the frame that is being processed with the second functional macro; and

the first monitor circuit and the second monitor circuit notifying each other of a result of the monitoring.

13. The image processing method according to claim 12 , wherein each functional macro divides each of the plurality of frames into a plurality of blocks and processes each block, and each functional macro immediately starts the processing of the next frame without performing an interruption process when the processing of all of the blocks in the preceding frame ends.

14. The image processing method according to claim 9 , further comprising:

overwriting the first processed image data of the preceding frame stored in the storage circuit with the first image processed image data of the next frame based on the number of the data line in the preceding frame that is being processed via the second functional macro.

15. The image processing method according to claim 9 , further comprising:

specifying a storage region storing the image data read via the second functional macro from the image data processed via the first functional macro; and

using the specified storage region as a vacant region to store image data after image processing the next frame.

16. The image processing method according to claim 9 , further comprising:

transferring final image data generated through sequential processing via a plurality of functional macros including the first and second functional macros from the storage circuit to an external storage.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0637 →
CHANGE OF NAME Recorded Jun 13, 2011
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 026436/0450 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024748/0328 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021977/0219 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 16, 2007
From: NAKAI, MOTOHIRO; FUKUOKA, TOMOHIRO
To: FUJITSU LIMITED
Reel/Frame 019752/0183 →
Priority Claims (1)
JP 2006-224301 · Aug 21, 2006 · national
Continuity (1)
Related Publication 20080044088A1 · Feb 21, 2008