Method and apparatus for digital error correction for binary successive approximation ADC
View Patent ↗An apparatus for digital error correction in a successive approximation (SAR) analog to digital converter (ADC) includes a binary weighted digital to analog converter (DAC) which can be virtually divided into multiple sub-DACs for redundancy insertion; and a comparator configured to compare the analog input with a DAC level corresponding to digital. The apparatus further includes a register and control logic unit configured to control a switching operation for DAC and to add output codes obtained from sub-DACs to output the added code as a final A/D converted code.
1. A method for correcting decision errors in a successive approximation (SAR) analog to digital converter (ADC), the method comprising:
controlling a digital to analog converter (DAC) with multiple sub-DACs of which one or more elements are shared by adjacent sub-DACs;
obtaining Most Significant Bits (MSBs) from a corresponding sub-DAC and its shared DAC element in the adjacent sub-DAC in such a way that the shared DAC element provides an intended offset while MSB-segment DAC (sub-DAC for MSBs) decides MSBs by a following binary decision algorithm;
making redundant decision after said obtaining the MSBs in such a way for a new DAC level to be a center of a determined analog range in a procedure for said obtaining MSBs by switching back the shared DAC element to the initial position (V CM ) and by re-arranging sub-DAC elements for said obtaining MSBs by using V CM as well as V REF and 0 as reference voltages;
obtaining Least Significant Bits (LSBs) from a LSB-segment DAC (sub-DAC for LSBs) by a following binary decision SAR process; and
adding digital codes obtained from a MSB-segment and a LSB-segment with code overlap to generate a final digital output code.
2. The method of claim 1 , wherein said controlling a DAC includes generating a necessary DAC level by re-arranging DAC element connections of upper sub-DAC for the redundant decision when lower sub-DAC starts to be used for a lower code decision.
3. The method of claim 1 , wherein said obtaining Most Significant Bits (MSBs) in each sub-DAC includes adding or subtracting an offset voltage of 0.5 LSB of the corresponding sub-DAC to or from an original DAC level in order to facilitate digital error correction.
4. The method of claim 3 , the lowest level sub-DAC does not conduct the operation of adding or subtracting an offset.
5. The method of claim 1 , wherein said obtaining Least Significant Bits (LSBs) from the LSB-segment DAC includes determining the DAC level to be the center of the previously predicted input range at beginning of decision.
6. The method of claim 1 , wherein said adding the digital output codes is performed by overlapping by one bit or more bits from two adjacent sub-DACs and by adding two output codes.