System and method for implementing a zero overhead loop
Systems and methods for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip are disclosed. The systems and methods include the use of a breakpoint mechanism which is additionally used in debugging in order to provide some of the looping functionality.
1. A system implemented on an integrated circuit chip for processing a sequence of instructions, the system comprising:
a program counter register configured to store an address for an instruction currently being processed;
a loop counter register configured to store a number of times to process the sequence of instructions;
a loop start register configured to store a reference to an address of a first instruction to execute within the sequence of instructions, wherein the reference to the address of the first instruction stored by the loop start register comprises an offset value that, when subtracted from the breakpoint address, results in the address of the first instruction of the sequence of instructions;
an existing breakpoint-match hardware within a microprocessor comprising:
a breakpoint register configured to store an address of a last instruction within the sequence of instructions, and
a comparator configured to compare the address stored in the breakpoint register with the address stored in the program counter register;
a pipeline comprising a plurality of pipeline stages; and
a branch-target cache configured to retrieve one or more subsequent instructions from a cache and to place the subsequent instructions in the pipeline in parallel with the instruction currently being processed, the one or more subsequent instructions being selected from a set of instructions beginning with the first instruction, if the address stored in the program counter register is not same as the address stored in the breakpoint register and a next value of the address stored in the program counter, corresponding to the program counter offset by an address, is same as the address stored in the breakpoint register, and the loop counter indicates that the sequence of instructions must be processed at least once more;
wherein the breakpoint-match hardware is configured to break execution of the sequence of instructions at the breakpoint and to set the program counter register to the address specified by the loop start register when the comparator determines that the address stored in the breakpoint register matches the address stored in the program counter register and the loop counter register indicates that the sequence of instructions must be processed at least once more.
2. The system of claim 1 , wherein the branch-target cache is configured to read the loop counter register to determine whether the sequence of instructions will be processed again and, if so, retrieves the one or more subsequent instructions selected from a second set of instructions.
3. The system of claim 1 , wherein the offset value comprises an absolute address value that is the address of the first instruction of the sequence of instructions, relative to the beginning of an address space.
4. An existing breakpoint mechanism within a microprocessor, comprising:
a breakpoint address register configured to store a location of a last instruction in a sequence of instructions;
a loop count register configured to store a number of times to process instructions in the sequence of instructions;
a loop start register configured to store a reference to a location of a first instruction in the sequence of instructions, wherein the reference to the location of the first instruction stored by the loop start register comprises an offset value that, when subtracted from the breakpoint address, results in the address of the first instruction of the sequence of instructions;
a comparator configured to compare a current address of a program counter to the contents of the breakpoint address register, and further configured to, when the address stored in the program counter matches the address stored in the breakpoint address register, break execution of the sequence of instructions at the address stored in the breakpoint address register and to transmit a message indicating that the address stored in the program counter matches the address stored in the breakpoint address register, the comparator further configured to, when the address stored in the program counter does not match the address stored in the breakpoint address register and the address stored in the program counter offset by an address matches the address stored in the breakpoint address register, retrieve one or more subsequent instructions from a cache and place the one or more subsequent instructions in a pipeline, the one or more subsequent instructions being selected from a set of instructions beginning with the first instruction of the sequence of instructions, if the loop count register indicates that the sequence of instructions must be processed at least once more; and
a branch logic that, responsive to receiving the message from the comparator, reads the loop count register to determine whether the loop should be processed again and, if so, reads the loop start register in order to determine the address of a next instruction for processing, and updates the program counter.