Phase-change memory device that stores information in a non-volatile manner by changing states of a memory material
A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.
1. A memory device comprising:
a substrate;
a plurality of memory cell arrays stacked above the substrate, each said memory cell array having bit lines coupled to one ends of memory cells and word lines coupled to the other ends of the memory cells, each said memory cell having a stacked structure of a variable resistance element and a diode, the memory cell arrays being partitioned in the bit line direction and in the word line direction into a plurality of cell blocks each serving as an access unit, each cell block including a plurality of the memory cells, a plurality of the bit lines, and a plurality of the word lines;
a bit line select circuit formed on the substrate to select one of the bit lines in one of the cell blocks; and
a word line select circuit formed on the substrate to select one of the word lines contained in one of the cell blocks.
2. The memory device according to claim 1 , wherein
the bit line select circuit comprises:
a plurality of sets of bit line select lines disposed in correspondence to a plurality of layers of the bit lines, respectively, each set being shared by a plurality of the cell blocks arranged in the word line direction, on which bit line driving signals are supplied;
a plurality of sets of bit line selecting transistors arranged in correspondence to the plurality of sets of bit line select lines to couple the bit line select lines to the corresponding bit lines in the cell blocks; and
a decode gate circuit configured to select one of the cell blocks arranged in the word line direction and drive the bit line selecting transistors belonging to selected one of the cell blocks.
3. The memory device according to claim 1 , wherein
the word line select circuit comprises:
a plurality of sets of word line select lines disposed in correspondence to a plurality of layers of the word lines, each set being shared by a plurality of the cell blocks arranged in the bit line direction, on which word line driving signals are supplied;
a plurality of sets of word line selecting transistors arranged in correspondence to the plurality of sets of the word line select lines to couple the word line select lines to the corresponding word lines in the cell blocks; and
a decode gate circuit configured to select one of the cell blocks arranged in the bit line direction and drive the word line selecting transistors belonging to selected one of the cell blocks.
4. The memory device according to claim 1 , wherein
adjacent two memory cell arrays share the word lines disposed therein.
5. The memory device according to claim 1 , wherein
adjacent two memory cell arrays share the bit lines disposed therein.