Method and apparatus for training the reference voltage level and data sample timing in a receiver
Methods and apparatuses for calculating the location of an optimal sampling point for a receiver system are disclosed. In brief, a first method comprises determining a maximum voltage margin and a maximum timing margin of a received signal, and from these margins, determining an optimal sampling point, which includes a reference voltage level (Vref) and a relative sample phase. The location of the optimal sampling point is based on the locations of the sampling point of the maximum voltage margin and the sampling point of the maximum timing margin. A second method comprises establishing an initial sampling point, and then successively refining each of the voltage and timing components of the sampling point until an optimal sampling point is reached.
1. A method for optimizing a sampling point of a signal in a receiver, comprising:
sampling the signal at a plurality of phases, and calculating a voltage margin at each of the plurality of phases;
determining a maximum voltage margin from the voltage margins and storing a first reference voltage level and a first phase value associated with the maximum voltage margin;
sampling the signal at a plurality of reference voltage levels, and calculating a timing margin at each of the plurality of reference voltage levels;
determining a maximum timing margin from the timing margins and storing a second reference voltage level and a second phase value associated with the maximum timing margin;
determining an optimal sampling point of the signal from the first and second phase values and the first and second reference voltage levels.
2. The method of claim 1 , wherein the maximum voltage margin comprises a maximum number of error-free reference voltage levels, and wherein each reference voltage level has at least one error-free phase value.
3. The method of claim 1 , wherein the maximum timing margin comprises a maximum number of error-free phase values, and wherein each phase value has at least one error-free reference voltage level.
4. The method of claim 1 , wherein calculating the voltage margin at each of the plurality of phases comprises, at each of the plurality of phases, comparing the signal to the reference voltage level while varying the plurality of reference voltage levels in each vertical direction.
5. The method of claim 1 , wherein calculating the timing margin at each of the plurality of reference voltage levels comprises, at each reference voltage level, comparing the signal to the reference voltage level while varying the plurality of phases in each horizontal direction.
6. The method of claim 1 , wherein each of the plurality of reference voltage levels comprises a voltage level output from a reference voltage circuit.
7. The method of claim 1 , wherein each of the plurality of reference voltage levels is formed by skewing a bias current in differential legs of the receiver.
8. The method of claim 1 , wherein the first reference voltage level and phase value are located at a midpoint of the maximum voltage margin, and wherein the second reference voltage level and phase value are located at a midpoint of the maximum timing margin.
9. The method of claim 1 , wherein the first and second phase values are averaged and the first and second reference voltage levels are averaged to determine the optimal sampling point of the signal.
10. A memory system for optimizing a sampling point of a signal, comprising:
a receiver for receiving and sampling the signal at a plurality of sampling points, each sampling point comprising a phase and a reference voltage level;
an error calculator for determining whether an error exists at each sampling point;
a state machine comprising executable instructions for:
calculating voltage margins based on output of the error calculator and storing a maximum voltage margin from the voltage margins, wherein the maximum voltage margin is associated with a first reference voltage level and a first phase value;
calculating timing margins based on output of the error calculator and storing a maximum timing margin from the timing margins, wherein the maximum timing margin is associated with a second reference voltage level and a second phase value;
adjusting the sampling point of the signal based on the first and second phase values and the first and second reference voltage levels.
11. The system of claim 10 , wherein a portion of the components of the memory system are repeated for each of a plurality of channels to provide independent and simultaneous channel training.
12. The system of claim 10 , wherein components of the memory system are shared across a plurality of channels to provide independent and sequential channel training.