Semiconductor memory device
A semiconductor memory device includes a sense amplifier that compares intensities of currents flowing through a first node and a second node with each other, a first MOSFET having a drain terminal connected with the first node, a second MOSFET having a drain terminal connected with the second node, a memory cell connected with a source terminal of the first MOSFET, and a reference cell. The semiconductor memory device further includes a connection control circuit that connects a source terminal of the second MOSFET with the reference cell at the time of a regular operation and connects the source terminal of the second MOSFET with a reference voltage terminal at the time of a test operation.
1. A semiconductor memory device comprising:
a sense amplifier that compares intensities of currents flowing through a first node and a second node with each other;
a first metal oxide semiconductor field effect transistor (MOSFET) having a drain terminal connected with the first node;
a second MOSFET having a drain terminal connected with the second node;
a memory cell connected with a source terminal of the first MOSFET;
a reference cell; and
a connection control circuit that connects a source terminal of the second MOSFET with the reference cell during a regular operation and connects the source terminal of the second MOSFET with a reference voltage terminal during a test operation,
wherein during a test operation of the memory cell, the semiconductor memory device supplies a test current that differs from a current during the regular operation to the second node by controlling a voltage of a gate terminal of the second MOSFET and compares the test current with a current that reflects a resistance state of the memory cell and is supplied to the first node.
2. The device according to claim 1 , wherein the connection control circuit has:
a switch circuit connected with the source terminal of the second MOSFET; and
a control circuit that controls to switch the reference cell connected with one contact of the switch circuit and the reference voltage terminal connected with the other contact depending on the regular operation and the test operation.
3. The device according to claim 1 , wherein the memory cell is formed of a magnetoresistive effect element and a select transistor connected in series, and
the magnetoresistive effect element is a resistance change element and configured to take at least two steady states in accordance with an internal magnetization state.
4. The device according to claim 3 , wherein the magnetoresistive effect element is formed by sequentially laminating a first ferromagnetic material layer having a fixed magnetizing direction, a non-magnetic material layer, and a second ferromagnetic material layer having a variable magnetizing direction.
5. The device according to claim 1 , wherein the reference cell is formed of a magnetoresistive effect element and a select transistor connected in series, and
the magnetoresistive effect element is a resistance change element and has an internal magnetization state that does not substantially vary.
6. The device according to claim 5 , wherein the magnetoresistive effect element is formed by sequentially laminating a first ferromagnetic material layer having a fixed magnetizing direction, a non-magnetic material layer, and a second ferromagnetic material layer having a fixed magnetizing direction.
7. A semiconductor memory device comprising:
a sense amplifier that compares intensities of currents flowing through a first node and a second node with each other;
a first metal oxide semiconductor field effect transistor (MOSFET) having a drain terminal connected with the first node;
a second MOSFET having a drain terminal connected with the second node;
a reference cell connected with a source terminal of the second MOSFET;
a memory cell; and
a connection control circuit that connects a source terminal of the first MOSFET with the memory cell during a regular operation and connects the source terminal of the first MOSFET with a reference voltage terminal during a test operation,
wherein during a test operation of the reference cell, the semiconductor memory device supplies a test current that differs from a current during the regular operation to the first node by controlling a voltage of a gate terminal of the first MOSFET and compares the test current with a current that reflects a resistance state of the reference cell and is supplied to the first node.
8. The device according to claim 7 , wherein the connection control circuit has:
a switch circuit connected with the source terminal of the first MOSFET; and
a control circuit that controls to switch the memory cell connected with one contact of the switch circuit and the reference voltage terminal connected with the other contact depending on the regular operation and the test operation.
9. The device according to claim 7 , wherein the memory cell is formed of a magnetoresistive effect element and a select transistor connected in series, and
the magnetoresistive effect element is a resistance change element and configured to take at least two steady states in accordance with an internal magnetization state.
10. The device according to claim 9 , wherein the magnetoresistive effect element is formed by sequentially laminating a first ferromagnetic material layer having a fixed magnetizing direction, a non-magnetic material layer, and a second ferromagnetic material layer having a variable magnetizing direction.
11. The device according to claim 7 , wherein the reference cell is formed of a magnetoresistive effect element and a select transistor connected in series, and
the magnetoresistive effect element is a resistance change element and has an internal magnetization state that does not substantially vary.
12. The device according to claim 11 , wherein the magnetoresistive effect element is formed by sequentially laminating a first ferromagnetic material layer having a fixed magnetizing direction, a non-magnetic material layer, and a second ferromagnetic material layer having a fixed magnetizing direction.
13. A semiconductor memory device comprising:
a sense amplifier that compares intensities of currents flowing through a first node and a second node with each other;
a first metal oxide semiconductor field effect transistor (MOSFET) having a drain terminal connected with the first node;
a second MOSFET having a drain terminal connected with the second node;
a memory cell;
a reference cell; and
a connection control circuit that connects a source terminal of the first MOSFET with the memory cell and connects a source terminal of the second MOSFET with a reference cell during a regular operation,
the connection control circuit connects the source terminal of the first MOSFET with the memory cell and connects the source terminal of the second MOSFET with a reference voltage terminal, or connects the source terminal of the second MOSFET with the reference cell and connects the source terminal of the first MOSFET with the reference voltage terminal during a test operation,
wherein during a test operation of the memory cell, the semiconductor memory device supplies a test current that differs from a current during the regular operation to the second node by controlling a voltage of a gate terminal of the second MOSFET and compares the test current with a current that reflects a resistance state of the memory cell and is supplied to the first node, and
wherein during a test operation of the reference cell, the semiconductor memory device supplies a test current that differs from a current during the regular operation to the first node by controlling a voltage of a gate terminal of the first MOSFET and compares the test current with a current that reflects a resistance state of the reference cell and is supplied to the first node.
14. The device according to claim 13 , wherein the connection control circuit has:
a switch circuit connected with the source terminal of the second MOSFET; and
a control circuit that controls to switch the reference cell connected with one contact of the switch circuit and the reference voltage terminal connected with the other contact depending on the regular operation and the test operation.
15. The device according to claim 13 , wherein the connection control circuit has:
a switch circuit connected with the source terminal of the first MOSFET; and
a control circuit that controls to switch the memory cell connected with one contact of the switch circuit and the reference voltage terminal connected with the other contact depending on the regular operation and the test operation.
16. The device according to claim 13 , wherein the memory cell is formed of a magnetoresistive effect element and a select transistor connected in series, and
the magnetoresistive effect element is a resistance change element and configured to take at least two steady states in accordance with an internal magnetization state.
17. The device according to claim 16 , wherein the magnetoresistive effect element is formed by sequentially laminating a first ferromagnetic material layer having a fixed magnetizing direction, a non-magnetic material layer, and a second ferromagnetic material layer having a variable magnetizing direction.
18. The device according to claim 13 , wherein the reference cell is formed of a magnetoresistive effect element and a select transistor connected in series, and
the magnetoresistive effect element is a resistance change element and has an internal magnetization state that does not substantially vary.
19. The device according to claim 18 , wherein the magnetoresistive effect element is formed by sequentially laminating a first ferromagnetic material layer having a fixed magnetizing direction, a non-magnetic material layer, and a second ferromagnetic material layer having a fixed magnetizing direction.