MIS field effect transistor and method for manufacturing the same
The MIS field-effect transistor includes: a substrate; a nitride semiconductor multilayer structure portion formed on the substrate, including a first group III-V nitride semiconductor layer of a first conductivity type, a second group III-V nitride semiconductor layer of a second conductivity type stacked thereon and a third group III-V nitride semiconductor layer of the first conductivity type stacked thereon; a gate insulating film formed on a wall surface formed over the first, second and third group III-V nitride semiconductor layers to extend over these first, second and third group III-V nitride semiconductor layers; a gate electrode made of a conductive material formed as being opposed to the second group III-V nitride semiconductor layer via the gate insulating film; a drawn portion electrically connected to the first group III-V nitride semiconductor layer and drawn from the nitride semiconductor multilayer structure portion in a direction parallel to the substrate; a drain electrode formed in contact with the drawn portion; and a source electrode electrically connected to the third group III-V nitride semiconductor layer.
1. The MIS field-effect transistor comprising:
a substrate;
a nitride semiconductor multilayer structure portion formed on the substrate, the nitride semiconductor multilayer structure portion including a first group III-V nitride semiconductor layer of a first conductivity type, a second group III-V nitride semiconductor layer of a second conductivity type stacked on the first group III-V nitride semiconductor layer, a third group III-V nitride semiconductor layer of the first conductivity type stacked on the second group III-V nitride semiconductor layer, a fourth group III-V nitride semiconductor layer of the first conductivity type formed between the substrate and the first group III-V nitride semiconductor layer, and a fifth group III-V nitride semiconductor layer formed between the substrate and the fourth group III-V nitride semiconductor layer;
a gate insulating film formed on a wall surface formed over the first, second and third group III-V nitride semiconductor layers to extend over the first, second and third group III-V nitride semiconductor layers;
a gate electrode made of a conductive material formed as being opposed to the second group III-V nitride semiconductor layer with the gate insulating film interposed therebetween;
a drawn portion electrically connected to the first group III-V nitride semiconductor layer and drawn from the nitride semiconductor multilayer structure portion in a direction parallel to the substrate;
a drain electrode formed in contact with the drawn portion; and
a source electrode electrically connected to the third group III-V nitride semiconductor layer;
wherein the source electrode is provided as being in contact with both of the second group III-V nitride semiconductor layer and the third group III-V nitride semiconductor layer.
2. The MIS field-effect transistor according to claim 1 , wherein
the fifth group III-V nitride semiconductor layer is an intrinsic semiconductor layer.
3. The MIS field-effect transistor according to claim 1 , wherein
the fifth group III-V nitride semiconductor layer is a layer doped with Mg, C or Fe.
4. The MIS field-effect transistor according to claim 1 , wherein
the drawn portion is an extension of the first group III-V nitride semiconductor layer.
5. The MIS field-effect transistor according to claim 1 , wherein
the substrate is an insulating substrate.
6. The MIS field-effect transistor according to claim 1 , wherein
a trench reaching the first group III-V nitride semiconductor layer is formed from the third group III-V nitride semiconductor layer through the second group III-V nitride semiconductor layer, and a sidewall of the trench forms the wall surface.
7. The MIS field-effect transistor according to claim 1 , wherein the first, second and third group III-V nitride semiconductor layers are stacked with major surfaces defined by C-planes.
8. The MIS field-effect transistor according to claim 1 , wherein the first, second and third group III-V nitride semiconductor layers are stacked with major surfaces defined by nonpolar planes or semipolar planes.
9. The MIS field-effect transistor according to claim 1 , wherein the wall surface of the first, second and third group III-V nitride semiconductor layers on which the gate insulating film is formed is defined by a nonpolar plane or a semipolar plane.
10. The MIS field-effect transistor according to claim 1 , wherein the substrate is a substrate having a region exhibiting a high dislocation density and a region exhibiting a small dislocation density in a direction along the substrate surface, and
the gate electrode is arranged to be opposed to a region grown from the region exhibiting a low dislocation density.
11. The MIS field-effect transistor according to claim 1 , wherein the gate insulating film is a nitride or an oxide.
12. The MIS field-effect transistor according to claim 1 , wherein the gate insulating film is made of silicon nitride or silicon oxide.
13. The MIS field-effect transistor according to claim 1 , wherein the conductive material constituting the gate electrode is made of a simple metal or an alloy containing at least any one of Al, Au and Pt.
14. The MIS field-effect transistor according to claim 1 , wherein the conductive material constituting the gate electrode contains polysilicon.
15. The MIS field-effect transistor according to claim 1 , wherein the source electrode or the drain electrode is made of a material containing at least Al.
16. The MIS field-effect transistor according to claim 1 , wherein the source electrode or the drain electrode is made of an alloy material containing at least Ti and Al.
17. The MIS field-effect transistor according to claim 1 , wherein the material constituting the source electrode or the drain electrode contains Mo or an Mo compound, Ti or a Ti compound, or W or a W compound.