Semiconductor memory device including repair redundancy memory cell arrays

1. A semiconductor memory device, comprising:

a plurality of memory cell matrixes, each of which contains a multiplicity of memory cell arrays whose number is larger than 2 n and smaller than 2 n+1 , n being a natural number, the multiplicity of memory cell arrays comprising 2 m normal memory cell arrays, m being a number of bits of an address, wherein a data access operation is performed on a normal memory cell in the normal memory cell arrays as a normal word line corresponding to the normal memory cell is activated in response to the address, and 2 n+1 −2 m dummy cell arrays; and

redundancy memory cell arrays for use in a repair operation,

wherein a first repair-expected memory cell in the normal memory cell arrays is replaced with a dummy cell included in the dummy cell arrays as a redundancy word line corresponding to the dummy cell is activated in response to an address corresponding to the first repair-expected memory cell,

wherein a second repair-expected memory cell in the normal memory cell arrays is replaced with a redundancy memory cell included in the redundancy memory cell arrays in response to an address corresponding to the second repair-expected memory cell, and

wherein the first repair-expected memory cell and the second repair-expected memory cell are disposed on the basis of a bit line sense amplifier.

2. The semiconductor memory device of claim 1 , wherein the plurality of memory cell matrixes includes an open bit line structure.

3. A semiconductor memory device, comprising:

a plurality of memory cell matrixes. each of which contains a multiplicity of memory cell arrays whose number is larger than 2 n and smaller than 2 n , n being a natural number. comprising first and second memory cell matrixes including 2 m memory cell arrays of the plurality of memory cell matrixes, m being a number of bits of an address, the first memory cell matrix and the second memory cell matrix being disposed on the basis of a bit line sense amplifier, and 2 n+1 −2 m dummy cell arrays of the plurality of memory cell matrixes; and

redundancy memory cell arrays for use in a repair operation,

wherein a first repair-expected memory cell in the first memory cell matrix is replaced with a redundancy memory cell included in the redundancy memory cell arrays in response to an address corresponding to the first repair-expected memory cell, and,

wherein a second repair-expected memory cell in the second memory cell matrix is replaced with a dummy memory cell in the dummy cell arrays in response to an address corresponding to the second repair-expected memory cell.

4. The semiconductor memory device of claim 3 , wherein a data access operation is performed on a normal memory cell in first and second memory cell matrixes as a normal word line corresponding to the normal memory cell in the first and second memory cell matrixes is activated in response to the address.

5. The semiconductor memory device of claim 4 , wherein the redundancy memory cell arrays are provided with data having the same polarity as that of data provided to the normal memory cell in the first memory cell matrixes.

6. The semiconductor memory device of claim 4 , wherein the dummy cell arrays are provided with data having the same polarity as that of data provided to the normal memory cell in the second memory cell matrixes.

7. The semiconductor memory device of claim 3 , wherein the first and second memory cell matrixes have an open bit line structure.

8. A method for repairing memory cell arrays in a semiconductor memory device,

the semiconductor memory device including a plurality of memory cell matrixes, each of which contains a multiplicity of memory cell arrays whose number is larger than 2 n and smaller than 2 n+1 , n being a natural number, and redundancy memory cell arrays for use in a repair operation,

the plurality of memory cell matrixes comprising normal memory cell arrays including 2 m memory cell arrays of the plurality of memory cell matrixes, m being a number of bits of an address, and dummy cell arrays including 2 n+1 −2 m memory cell arrays of the plurality of memory cell matrixes, and

the normal cell arrays being divided into even memory cell matrixes and odd memory cell matrixes, the even memory cell matrixes and the odd memory cell matrixes being disposed in different memory cell matrixes of the normal memory cell arrays on the basis of a bit line sense amplifier,

the method comprising:

replacing a first repair-expected memory cell in the normal memory cell arrays with a memory cell included in the dummy cell arrays; and

replacing a second repair-expected memory cell in the normal memory cell arrays with a memory cell included in the redundancy cell arrays,

wherein the first repair-expected memory cell is included in one of even and odd memory cell matrixes, and the second repair-expected memory cell is included in the other of even and odd memory cell matrixes.

9. The method of claim 8 , wherein the memory cell matrixes have an open bit line structure.

10. The method of claim 9 , wherein the redundancy memory cell arrays are provided with data having the same polarity as that of data provided to the normal memory cell in the even memory cell matrixes.

11. The method of claim 9 , wherein the dummy cell arrays are provided with data having the same polarity as that of data provided to the normal memory cell in the odd memory cell matrixes.