Table-based DFM for accurate post-layout analysis
View Patent ↗Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
1. An integrated circuit (IC) design method for post-layout analysis to an IC device, the method comprising:
providing a computer system having a microprocessor, wherein the computer system receives instructions that when executed, carry out:
receiving a design layout of a IC device;
extracting equivalent dimensions of the IC device based on the design layout;
calculating electrical performance parameters of the IC device using a data refinement table and the equivalent dimensions; and
tuning the design layout of the IC device corresponding to the calculated electrical performance parameters of the IC device.
2. The method of claim 1 , wherein the extracting of the equivalent dimensions comprises:
generating an IC contour based on the design layout by shape simulation; and
calculating equivalent dimensions from the IC contour.
3. The method of claim 2 , wherein the generating of the IC contour comprises generating a channel region of the IC device.
4. The method of claim 2 , wherein the calculating of the equivalent dimensions comprises:
finding an equivalent rectangle to represent an overlapping region of an active region and a gate electrode of the IC device; and
extracting equivalent width and length of the equivalent rectangle.
5. The method of claim 1 , wherein the calculating of the electrical performance parameters further comprises using a shape related model.
6. The method of claim 5 , wherein the data refinement table comprises various electrical parameters associated with the shape related model.
7. A method, comprising:
deriving equivalent dimensions of an integrated circuit (IC) device based on its design layout;
generating a data refinement table;
obtaining electrical performance parameters of the IC device based on the equivalent dimensions and the data refinement table; and
thereafter adjusting the design layout of the IC device based on the electrical performance parameters;
wherein the deriving, the generating, the obtaining, and the adjusting are each carried out using a computer hardware device encoded with software instructions.
8. The method of claim 7 , wherein the deriving the equivalent dimensions includes:
generating a contour of the IC device through simulation; and
computing the equivalent dimensions based on the IC contour.
9. The method of claim 8 , wherein the generating the contour includes defining a channel contour.
10. The method of claim 9 , wherein the generating the contour includes generating an active region contour and a gate electrode contour, and wherein the channel contour is defined by an overlapping portion of the active region contour and the gate electrode contour.
11. The method of claim 10 , wherein the overlapping region has a rectangular shape that includes a width and a length, and wherein the computing the equivalent dimensions is carried out using the width and the length.
12. The method of claim 7 , wherein the obtaining the electrical performance parameters is carried out using a shape related model.
13. The method of claim 12 , further including predicting actual electrical performance of the IC device based on the shape related model.
14. The method of claim 12 , wherein the generating the data refinement table is carried out in a manner so that the data refinement table includes electrical parameters that are associated with the shape related model.
15. An apparatus comprising a non-transitory, tangible computer readable storage medium storing a computer program, wherein the computer program has instructions that when executed, carry out:
deriving equivalent dimensions of an integrated circuit (IC) device based on its design layout;
generating a data refinement table;
obtaining electrical performance parameters of the IC device based on the equivalent dimensions and the data refinement table; and
thereafter adjusting the design layout of the IC device based on the electrical performance parameters.
16. The apparatus of claim 15 , wherein the instructions for deriving the equivalent dimensions include instructions for:
generating a contour of the IC device through simulation; and
computing the equivalent dimensions based on the IC contour.
17. The apparatus of claim 16 , wherein the instructions for generating the contour include instructions for:
generating an active region contour and a gate electrode contour; and
defining an overlapping portion of the active region contour and the gate electrode contour as a channel contour.
18. The apparatus of claim 15 , wherein the instruction for obtaining the electrical performance parameters include instructions for using a shape related model.
19. The apparatus of claim 18 , wherein the computer program further includes instructions for predicting actual electrical performance of the IC device based on the shape related model.
20. The apparatus of claim 18 , wherein the instructions for generating the data refinement table include instructions that associate electrical parameters of the data refinement table with the shape related model.