IP Library › Granted Patent US 8,007,627
Granted Patent B2
US 8,007,627 · App. 11/064,122 · Granted Aug 30, 2011

Electronic component mounting method and apparatus

Assignee: Panasonic Corporation
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Quick Facts
Patent No.
US 8,007,627
App. No.
11/064,122
Granted
Aug 30, 2011
Kind
B2
Abstract

A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip is corrected and the board is connected, the bumps are compressed, and the insulating resin is hardened.

Claims (10)

1. A method of mounting an electronic component comprising:

forming a ball at a tip of a metal wire;

forming a pointed bump by thermocompression-bonding the ball to a first electrode of an electronic component;

positioning an insulating resin layer comprising a mixture of an insulating resin and an inorganic filler, between the electronic component and a circuit board while the first electrode is aligned with a second electrode of the circuit board; and

bonding, without leveling the pointed bump before the pointed bump is brought into contact with the second electrode of the circuit board, the electronic component to the circuit board by hardening the insulating resin layer such that the first electrode becomes electrically connected to the second electrode via the pointed bump, and such that the inorganic filler is forced outwardly of the pointed bump by virtue of the pointed bump entering the insulating resin layer at a beginning of said bonding operation,

wherein the insulating resin layer comprises:

a first resin layer in contact with the electronic component;

a second resin layer in contact with the first resin layer; and

a third resin layer in contact with the circuit board, and

wherein each of the first resin layer and the third resin layer includes an insulating resin that is identical, and the second resin layer has an amount of the inorganic filler that is less than an amount of the inorganic filler in each of the first resin layer and the third resin layer.

Priority Claims (2)
JP 11-21800 · Jan 29, 1999 · national
JP 11-22015 · Jan 29, 1999 · national
Continuity (2)
Division 09890066
Related Publication 20050155706A1 · Jul 21, 2005