Bootstrap circuit that may be used in a shift register or output buffer

1. A bootstrap circuit configured to employ first, second and third transistors of the same conduction type wherein:

(A-1) a specific one of the source and drain areas of said first transistor and a specific one of the source and drain areas of said second transistor are connected to each other by an output section of said bootstrap circuit;

(A-2) the other one of said source and drain areas of said first transistor is directly electrically connected to a clock supply line which conveys a specific one of two clock signals having phases different from each other;

(A-3) the gate electrode of said first transistor and a specific one of the source and drain areas of said third transistor are connected to each other by a node section;

(B-1) the other one of said source and drain areas of said second transistor is connected to a first voltage supply line which conveys a first predetermined voltage;

(C-1) the other one of said source and drain areas of said third transistor is connected to a signal supply line which conveys an input signal supplied to said bootstrap circuit;

(C-2) the gate electrode of said third transistor is directly electrically connected to a clock supply line which conveys the other one of said two clock signals;

the gate electrode of said second transistor is directly electrically connected to said clock supply line which conveys said other one of said two clock signals; and

a voltage-variation repression capacitor is provided between said node section and said first voltage supply line.

2. A bootstrap circuit comprising a first transistor, a second transistor, a third transistor, and a voltage-variation repression capacitor, wherein:

a first source/drain area of the first transistor is connected to a first source/drain area of the second transistor, the first source/drain area of the first transistor and the first source/drain area of the second transistor being connected to an output section of the bootstrap circuit;

a second source/drain area of the first transistor is directly electrically connected to a first clock supply line;

a second source/drain area of the second transistor is connected to a first voltage supply line;

a gate electrode of the second transistor is directly electrically connected to a second clock supply line;

a gate electrode of the first transistor is connected to a first source/drain area of the third transistor by a node section;

a second source/drain area of the third transistor is connected to a signal supply line, the signal supply line conveying an input signal supplied to the bootstrap circuit;

a gate electrode of the third transistor is directly electrically connected to the second clock supply line; and

the voltage-variation repression capacitor is connected between the node section and the first voltage supply line.

3. The bootstrap circuit according to claim 2 , wherein the first transistor, the second transistor, and the third transistor are of a same conduction type.

4. The bootstrap circuit according to claim 2 , wherein the first voltage supply line conveys a first predetermined voltage.

5. The bootstrap circuit according to claim 2 , wherein the first clock supply line conveys a first clock signal and the second clock supply line conveys a second clock signal, the first clock signal having a phase different than a phase of the second clock signal.

6. The bootstrap circuit according to claim 5 , wherein the voltage-variation repression capacitor has a capacitance such that electric-potential variations caused by abrupt changes generated by the first clock signal and abrupt changes generated by the second clock signal cancel each other.