Systems and methods for controlling a DC motor
Various systems and methods for controlling DC motors are disclosed herein. For example, one method provides for controlling a polyphase, brushless DC motor. The method includes providing a DC motor that has a plurality of phases. Such a DC motor operates by inducing a current in the plurality of phases in accordance with a plurality of commutation states. In the example, six commutation states are discussed, but fewer than or more than six commutation states may exist. The method further includes initializing a count, inducing a current in the plurality of phases in accordance with a first commutation state, and incrementing the count until the current achieves a threshold in the first commutation state. Then, a current is induced in the plurality of phases in accordance with a second commutation state, and the count is decremented until the current achieves the threshold in the second commutation state. The sign bit of the count is stored, and a desired initial commutation state is determined based at least in part on the sign bit of the count.
1. A DC motor controller, the controller comprising:
a period detector, wherein the period detector is operable to detect a period associated with a DC motor, wherein the DC motor includes a plurality of phases to which current is applied in accordance with a plurality of commutation states, and wherein the plurality of commutation states includes at least a first commutation state and a second commutation state;
an initial commutation state controller, wherein the initial commutation state controller is operable to:
initialize an up/down counter;
induce a first current in the plurality of phases in accordance with the first commutation state;
increment the up/down counter until the first current achieves a threshold in the first commutation state;
induce a second current in the plurality of phases in accordance with the second commutation state;
decrement the up/down counter until the second current achieves the threshold in the second commutation state;
store the sign bit of the up/down counter; and
determine a desired initial commutation state based at least in part on the sign bit of the up/down count.
2. The controller of claim 1 , wherein the first commutation state and the second commutation state form a first commutation state pair; wherein storing the sign bit of the count includes storing the sign bit as a first sign bit associated with the first commutation pair; wherein the plurality of commutation states further includes a third commutation state, a fourth commutation state, a fifth commutation state and a sixth commutation state; wherein the third commutation state and the fourth commutation state form a second commutation state pair; wherein the fifth commutation state and the sixth commutation state form a third commutation state pair, and wherein the initial commutation state controller is further operable to:
initialize the up/down counter;
induce a third current in the plurality of phases in accordance with the third commutation state;
increment the up/down counter until the third current achieves a threshold in the third commutation state;
induce a fourth current in the plurality of phases in accordance with the fourth commutation state;
decrement the up/down counter until the fourth current achieves the threshold in the fourth commutation state;
store the sign bit of the up/down counter, wherein the sign bit is stored as a second sign bit associated with the second commutation pair;
induce a fifth current to the plurality of phases in accordance with the fifth commutation state;
increment the up/down counter until the fifth current achieves a threshold in the fifth commutation state;
induce a sixth current to the plurality of phases in accordance with the sixth commutation state;
decrement the up/down counter until the sixth current achieves the threshold in the sixth commutation state;
store the sign bit of the up/down counter, wherein the sign bit is stored as a third sign bit associated with the third commutation pair; and
determine a desired initial commutation state based at least in part on the first sign bit, the second sign bit and the third sign bit.
3. The controller of claim 2 , wherein the controller further includes a sign bit register, and wherein the first sign bit, the second sign bit and the third sign bit are arranged as a three bit array in the sign bit register, and wherein determining the desired initial commutation state includes decoding the three bit array.
4. The method of claim 3 , wherein determining the desired initial commutation state further includes determining the current commutation state, and wherein the desired initial commutation state is at least one commutation state after the current commutation state.
5. A method for controlling a polyphase, brushless DC motor, the method comprising:
providing a DC motor, wherein the DC motor includes a plurality of phases, wherein operating the DC motor includes inducing currents in the plurality of phases in accordance with a plurality of commutation states, and wherein the plurality of commutation states includes at least a first commutation state and a second commutation state;
initializing a count;
inducing a first current to the plurality of phases in accordance with the first commutation state;
incrementing the count until the current achieves a threshold in the first commutation state;
inducing a second current to the plurality of phases in accordance with the second commutation state;
decrementing the count until the second current achieves the threshold in the second commutation state;
storing the sign bit of the count; and
determining a desired initial commutation state based at least in part on the sign bit of the count.
6. The method of claim 5 , wherein inducing the first current in accordance with the first commutation state and incrementing the count, and inducing the second current in accordance with the second commutation state and decrementing the count is repeated a programmable number of times before storing the sign bit of the count.
7. The method of claim 6 , wherein the programmable number of times is sixteen.
8. The method of claim 5 , wherein the first commutation state and the second commutation state form a first commutation state pair; wherein storing the sign bit of the count includes storing the sign bit as a first sign bit associated with the first commutation pair; wherein the plurality of commutation states further includes a third commutation state, a fourth commutation state, a fifth commutation state and a sixth commutation state; wherein the third commutation state and the fourth commutation state form a second commutation state pair; and wherein the fifth commutation state and the sixth commutation state form a third commutation state pair, the method further comprising:
initializing the count;
inducing a third current in the plurality of phases in accordance with the third commutation state;
incrementing the count until the third current achieves a threshold in the third commutation state;
inducing a fourth current in the plurality of phases in accordance with the fourth commutation state;
decrementing the count until the fourth current achieves the threshold in the fourth commutation state;
storing the sign bit of the count, wherein the sign bit is stored as a second sign bit associated with the second commutation pair;
inducing a fifth current in the plurality of phases in accordance with the fifth commutation state;
incrementing the count until the fifth current achieves a threshold in the fifth commutation state;
inducing a sixth current in the plurality of phases in accordance with the sixth commutation state;
decrementing the count until the sixth current achieves the threshold in the sixth commutation state; and
storing the sign bit of the count, wherein the sign bit is stored as a third sign bit associated with the third commutation pair.
9. The method of claim 8 , wherein the method further comprises:
determining a desired initial commutation state based at least in part on the first sign bit, the second sign bit and the third sign bit.
10. The method of claim 8 , wherein:
inducing the first current in accordance with the first commutation state and incrementing the count, and inducing the second current in accordance with the second commutation state and decrementing the count is repeated a programmable number of times before storing the first sign bit;
inducing the third current in accordance with the third commutation state and incrementing the count, and inducing the fourth current in accordance with the fourth commutation state and decrementing the count is repeated the programmable number of times before storing the second sign bit; and
inducing the fifth current in accordance with the fifth commutation state and incrementing the count, and inducing the sixth current in accordance with the sixth commutation state and decrementing the count is repeated a programmable number of times before storing the third sign bit.
11. The method of claim 10 , wherein the programmable number of times is sixteen.
12. The method of claim 6 , wherein the first sign bit, the second sign bit and the third sign bit are arranged in a three bit array, and wherein determining the desired initial commutation state includes decoding the three bit array.
13. The method of claim 12 , wherein determining the desired initial commutation state further includes determining the current commutation state, and wherein the desired initial commutation state is at least one commutation state after the current commutation state.
14. A DC motor system, the system comprising:
a DC motor, wherein the DC motor includes a plurality of phases, wherein operating the DC motor includes applying a voltage to the plurality of phases in accordance with a plurality of commutation states, and wherein the plurality of commutation states includes at least a first commutation state and a second commutation state;
an initial commutation state controller, wherein the initial commutation state controller includes an up/down counter, and wherein the initial commutation state controller is operable to:
initialize the up/down counter;
apply a voltage to the plurality of phases in accordance with the first commutation state;
increment the up/down counter until a first current corresponding to the voltage achieves a threshold in the first commutation state;
apply the voltage to the plurality of phases in accordance with the second commutation state;
decrement the up/down counter until a second current corresponding to the voltage achieves the threshold in the second commutation state;
store the sign bit of the up/down counter; and
determine a desired initial commutation state based at least in part on the sign bit of the up/down counter.
15. The system of claim 14 , wherein applying the voltage in accordance with the first commutation state and incrementing the up/down counter, and applying the voltage in accordance with the second commutation state and decrementing the up/down counter is repeated a programmable number of times before storing the sign bit of the up/down counter.
16. The system of claim 15 , wherein the programmable number of times is sixteen.
17. The system of claim 14 , wherein the first commutation state and the second commutation state form a first commutation state pair; wherein storing the sign bit of the up/down counter includes storing the sign bit as a first sign bit associated with the first commutation pair; wherein the plurality of commutation states further includes a third commutation state, a fourth commutation state, a fifth commutation state and a sixth commutation state; wherein the third commutation state and the fourth commutation state form a second commutation state pair; wherein the fifth commutation state and the sixth commutation state form a third commutation state pair, and wherein the initial commutation state controller is operable to:
initialize the up/down counter;
apply the voltage to the plurality of phases in accordance with the third commutation state;
increment the count until a third current corresponding to the voltage achieves a threshold in the third commutation state;
apply the voltage to the plurality of phases in accordance with the fourth commutation state;
decrement the up/down counter until a fourth current corresponding to the voltage achieves the threshold in the fourth commutation state;
store the sign bit of the up/down counter, wherein the sign bit is stored as a second sign bit associated with the second commutation pair;
apply the voltage to the plurality of phases in accordance with the fifth commutation state;
increment the up/down counter until a fifth current corresponding to the voltage achieves a threshold in the fifth commutation state;
apply the voltage to the plurality of phases in accordance with the sixth commutation state;
decrement the up/down counter until a sixth current corresponding to the voltage achieves the threshold in the sixth commutation state; and
store the sign bit of the up/down counter, wherein the sign bit is stored as a third sign bit associated with the third commutation pair.
18. The system of claim 17 , wherein the initial commutation state controller is operable to:
determine a desired initial commutation state based at least in part on the first sign bit, the second sign bit and the third sign bit.
19. The system of claim 16 , wherein the system further includes a sign bit register, and wherein the first sign bit, the second sign bit and the third sign bit are arranged as a three bit array in the sign bit register, and wherein determining the desired initial commutation state includes decoding the three bit array.
20. The system of claim 19 , wherein determining the desired initial commutation state further includes determining the current commutation state, and wherein the desired initial commutation state is at least one commutation state after the current commutation state.
21. The system of claim 17 , wherein determining that a current threshold has been achieved is accomplished by sensing a voltage drop across a transistor.