Adaptive radio transceiver with a power amplifier
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
1. An integrated circuit transistor structure that amplifies a radio frequency signal in a circuit having a reference DC voltage to obtain an amplified radio frequency signal to an output that has a load associated therewith comprising:
a first FET transistor having a first source connected to ground and a first gate that receives the radio frequency signal; and
a second FET transistor having a second source connected to a first drain of the first FET transistor, a second gate connected, via a first resistor, to the reference DC voltage that biases the second gate, and a second drain that is connected to the reference DC voltage via an inductor, the second FET transistor being a cascoded transistor, an output of the cascoded transistor being connected to the reference DC voltage through the inductor,
wherein a shunt capacitor provides a path to the ground for the first gate, wherein the inductor is in parallel with a circuital arrangement comprising a second resistor in series with a switch, and wherein the first resistor reduces an effect caused by a parasitic inductance at the second gate of the cascoded transistor.
2. The transistor structure according to claim 1 , wherein the reference DC voltage is Vdd, and wherein the first resistor provides a shared path to the reference DC voltage for a third gate of a second cascoded transistor.
3. The transistor structure according to claim 1 , wherein the transistor structure is part of a receiver of a wireless communications device, wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device supports spread spectrum communications.
4. The transistor structure according to claim 1 , further comprising other CMOS transceiver chip components on the integrated circuit.
5. The transistor structure according to claim 3 , wherein the receiver is part of a single integrated circuit chip transceiver.
6. The transistor structure according to claim 1 , wherein the transistor structure is part of a single integrated circuit transceiver of a wireless communications device, wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device supports direct sequence spread spectrum modulation.
7. The transistor structure according to claim 1 , wherein the transistor structure is part of a single integrated circuit transceiver of a wireless communications device, wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device supports frequency hopping.
8. The transistor structure according to claim 1 , wherein the transistor structure is part of a receiver of a wireless communications device, wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device supports orthogonal frequency division multiplexing.
9. The transistor structure according to claim 1 , wherein the first source is configured for inductive degeneration.
10. The transistor structure according to claim 1 , wherein the transistor structure is part of a wireless communications device, and wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device supports Bluetooth communications.
11. The transistor structure according to claim 1 , wherein the integrated circuit transistor structure is part of a low noise amplifier (LNA) of a receiver, and wherein the LNA is tuned such that the inductor, LNA output parasitic capacitance and an input capacitance of a next stage resonate.
12. An integrated circuit transistor structure that amplifies a radio frequency signal in a circuit having a reference DC voltage to obtain an amplified radio frequency signal to an output that has a load associated therewith comprising:
a first transistor having a first source connected to ground and a first gate that receives the radio frequency signal; and
a second transistor having a second source connected to a first drain of the first transistor, a second gate connected, via a first resistor, to the reference DC voltage that biases the second gate, and a second drain that is connected to the reference DC voltage via an inductor, the second transistor being a cascoded transistor, an output of the cascoded transistor being connected to the reference DC voltage through the inductor,
wherein the first resistor provides a shared path to the reference DC voltage for a third gate of a second cascoded transistor, wherein a shunt capacitor provides a path to the ground for the first gate, wherein the inductor is in parallel with a circuital arrangement comprising a second resistor in series with a switch, and wherein the first resistor reduces an effect caused by a parasitic inductance at the second gate of the cascoded transistor.
13. The transistor structure according to claim 12 , wherein the transistor structure is part of a cascoded differential pair with inductive degeneration.
14. The transistor structure according to claim 12 , wherein the transistor structure is part of a wireless communications device, wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device supports wireless local area network communications.
15. The transistor structure according to claim 12 , wherein the transistor structure is part of a low noise amplifier (LNA) of a receiver, and wherein the LNA is tuned such that the inductor, LNA output parasitic capacitance and an input capacitance of a next stage resonate.
16. The transistor structure according to claim 12 , wherein the transistor structure is part of a single integrated circuit transceiver of a wireless communications device, wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device supports orthogonal frequency division multiplexing.
17. The transistor structure according to claim 12 , wherein the transistor structure is part of a single integrated circuit transceiver of a wireless communications device, wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device supports direct sequence spread spectrum modulation.
18. The transistor structure according to claim 12 , wherein the transistor structure is part of a wireless communications device, wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device supports Bluetooth communications.
19. An integrated circuit transistor structure that amplifies a radio frequency signal in a circuit having a reference DC voltage to obtain an amplified radio frequency signal to an output that has a load associated therewith comprising:
a first FET transistor having a first source connected to ground and a first gate that receives the radio frequency signal; and
a second FET transistor having a second source connected to a first drain of the first FET transistor, a second gate connected, via a first resistor, to the reference DC voltage that biases the second gate, and a second drain that is connected to the reference DC voltage via an inductor, the second FET transistor being a cascoded transistor, an output of the cascoded transistor being connected to the reference DC voltage through the inductor, the load including circuitry disposed between the reference DC voltage and the second drain of the second FET transistor,
wherein the transistor structure is part of a cascoded differential pair with inductive degeneration, wherein the first resistor provides a shared path to the reference DC voltage for a third gate of a second cascoded transistor, wherein a shunt capacitor provides a path to the ground for the first gate, wherein the inductor is in parallel with a circuital arrangement comprising a second resistor in series with a switch.
20. The transistor structure according to claim 19 , wherein the transistor structure is part of a wireless communications device, wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device performs orthogonal frequency division multiplexing.
21. The transistor structure according to claim 19 , wherein the transistor structure is part of a wireless communications device, wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device performs spread spectrum modulation.
22. The transistor structure according to claim 19 , wherein the transistor structure is part of a wireless communications device, wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device performs frequency hopping.
23. The transistor structure according to claim 19 , wherein the transistor structure is part of a wireless communications device, wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device supports wireless communications using orthogonal frequency division multiplexing and wireless communications using spread spectrum modulation.
24. The transistor structure according to claim 19 , wherein the transistor structure is part of a wireless communications device, wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device supports wireless communications using direct sequence spread spectrum modulation and wireless communications using orthogonal frequency division multiplexing.
25. The transistor structure according to claim 19 , wherein the transistor structure is part of a receiver in a wireless communications device in which the wireless communications device comprises a transmitter and the receiver, the transmitter and the receiver being integrated on a single integrated circuit chip.
26. An integrated circuit transistor structure that amplifies a radio frequency signal in a circuit having a reference DC voltage to obtain an amplified radio frequency signal to an output that has a load associated therewith comprising:
a first transistor having a first source connected to ground and a first gate that receives the radio frequency signal; and
a second transistor having a second source connected to a first drain of the first transistor, a second gate connected, via a first resistor, to the reference DC voltage that biases the second gate, and a second drain that is connected to the reference DC voltage via an inductor, the second transistor being a cascoded transistor, an output of the cascoded transistor being connected to the reference DC voltage through the inductor, wherein first resistor provides a shared path to the reference DC voltage for a third gate of a second cascoded transistor, wherein a shunt capacitor provides a path to the ground for the first gate, wherein the inductor is in parallel with a circuital arrangement comprising a second resistor in series with a switch, and wherein the first resistor reduces an effect caused by a parasitic inductance at the second gate of the cascoded transistor,
wherein the first transistor and the second transistor are part of a cascoded differential pair with inductive degeneration, wherein the load includes circuitry that is directly connected to the reference DC voltage and to the second drain of the second FET transistor, wherein the first transistor and the second transistor are part of a low noise amplifier (LNA) that receives the radio frequency signal, wherein the LNA is tuned such that the inductor, LNA output parasitic capacitance and an input capacitance of a next stage resonate, wherein the LNA is part of a receiver of a wireless communications device, wherein the wireless communications device is configured to support a plurality of wireless communication standards, and wherein the wireless communications device supports spread spectrum communications.