Semiconductor device and semiconductor integrated circuit

1. A semiconductor integrated circuit, comprising:

a semiconductor substrate;

a circuit formed on the semiconductor substrate; and

a plurality of pads arranged in a linearly juxtaposed relationship with each other in a direction perpendicular to a peripheral edge side of the semiconductor substrate which is nearest to the pads on a main face of the semiconductor substrate and electrically connected to the circuit in a corresponding relationship to a signal, a power supply voltage and a reference signal; wherein

the signal pads for inputting and outputting the signal being arranged farthest from the peripheral edge side of the semiconductor substrate in each of rows of the pads in which the pads are juxtaposed linearly.

2. The semiconductor integrated circuit according to claim 1 , wherein

the power supply voltage pad, reference voltage pad and signal pad in each pad row are arranged in order from the side nearer to the peripheral edge side of the semiconductor substrate.

3. The semiconductor integrated circuit according to claim 1 , wherein

a plurality of pad rows are arranged along the peripheral edge side of the semiconductor substrate, and

in the plural pad rows, a plurality of reference voltage pads are disposed at positions which surround three sides of one of the signal pads.

4. A semiconductor device, comprising:

a semiconductor substrate having a circuit formed thereon;

a mounting substrate cemented to a rear face of the semiconductor substrate;

a plurality of pads arranged in a linearly juxtaposed relationship with each other in a direction perpendicular to a peripheral edge side of the semiconductor substrate which is nearest to the pads on a main face of the semiconductor substrate and electrically connected to the circuit in a corresponding relationship to a signal, a power supply voltage and a reference signal;

a plurality of wires individually cemented at one end thereof to the pads; and

a plurality of wire cemented elements formed on the mounting substrate and cemented to the other end of the wires; wherein

the signal pads for inputting and outputting the signal being arranged farthest from the peripheral edge side of the semiconductor substrate in each of rows of the pads in which the pads are juxtaposed linearly,

the signal wire cemented elements for inputting and outputting the signal from among the wire cemented elements being arranged at a position on the mounting substrate which is positioned farther from the semiconductor substrate than the other wire cemented elements.

5. The semiconductor device according to claim 4 , wherein

the wires for connecting the pads and the wire cemented elements in a one-by-one corresponding relationship to each other bridge the pads and the wire cemented elements in different loop heights thereamong.

6. The semiconductor device according to claim 5 , wherein

the wires are arranged in different loop heights along a direction of an extension line of a straight line which interconnects the centers of the pads in each pad row.

7. The semiconductor device according to claim 4 , wherein

the power supply voltage pad, reference voltage pad and signal pad in each pad row are arranged in order from the side nearer to the peripheral edge side of the semiconductor substrate, and

the power supply voltage wire cemented element, reference voltage wire cemented element and signal wire cemented element to be electrically connected to the power supply voltage pad, reference voltage pad and signal pad, respectively, in each pad row individually by wires are positioned so as to be farther in order from the peripheral edge side of the semiconductor substrate.

8. The semiconductor device according to claim 7 , wherein

the wires for connecting the pads and the wire cemented elements in a one-by-one corresponding relationship to each other bridge the pads and the wire cemented elements in different loop heights thereamong, and the wires for propagating the signal, reference potential and power supply voltage are arranged in a descending order of the loop height.

9. The semiconductor device according to claim 8 , wherein

the wires are arranged in different loop heights along a direction of an extension line of a straight line which interconnects the centers of the pads in each pad row.

10. The semiconductor device according to claim 7 , wherein

a plurality of pad rows are arranged along the peripheral edge side of the semiconductor substrate, and

the power supply voltage wire cemented elements and the reference voltage wire cemented elements are individually formed as a single belt-shaped conductive layer common to the plural pad rows on the mounting substrate.

11. The semiconductor device according to claim 10 , wherein

a plurality of pad rows are arranged along the peripheral edge side of the semiconductor substrate, and

in the plural pad rows, a plurality of reference voltage pads are disposed at positions which surround three sides of one of the signal pads.

12. The semiconductor device according to claim 11 , wherein

the signal wire cemented element is surrounded on the three sides thereof by the reference voltage wire cemented element formed from a single belt-shaped conductor layer and two branch portions branching from the reference voltage wire cemented element.

13. The semiconductor device according to claim 7 , wherein

a plurality of pad rows are arranged along the peripheral edge side of the semiconductor substrate, and

in the plural pad rows, a plurality of reference voltage pads are disposed at positions which surround three sides of one of the signal pads.