Local charge and work function engineering on MOSFET
View Patent ↗The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.
1. A semiconductor device, comprising:
a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to the drain; and
a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region, wherein the gate stack includes:
a high k dielectric layer disposed on the semiconductor substrate;
a first metal feature disposed on the high k dielectric layer, the first metal feature having a first work function and defining a second dimension parallel with the first dimension; and
a second metal feature doped with impurities to have a second work function close to a band edge of an energy band and different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.
2. The device of claim 1 , wherein the first work function is close to a mid gap of an energy band.
3. The device of claim 1 , wherein the second metal feature is disposed on the first metal feature.
4. The device of claim 1 , wherein the second feature is partially embedded in the first metal feature.
5. The device of claim 1 , further comprising a gate electrode disposed on the second metal feature.
6. The device of claim 1 , further comprising: a first spacer formed on sidewalls of the gate stack; and
a seal spacer interposed between the gate stack and the first spacer and being functional to seal the high k dielectric material layer and the first metal feature.
7. The device of claim 1 , further comprising a buffer layer interposed between the high k dielectric material layer and the first metal feature.
8. The device of claim 1 , further comprising an interfacial layer interposed between the semiconductor substrate and the high k dielectric material layer.
9. A semiconductor device, comprising:
a high k dielectric layer disposed on a semiconductor substrate;
a first metal feature having a first work function and disposed on the high k dielectric layer;
a second metal feature doped with impurities to have a second work function close to a band edge of an energy band and different from the first work function and embedded in the first metal feature; and
a gate electrode disposed on the second metal feature.
10. The device of claim 9 , wherein the first metal feature is horizontally extruded from the gate electrode.
11. The device of claim 10 , further comprising a seal spacer formed on the extrude portion of the first metal feature and on sidewalls of the first metal feature and the gate electrode.
12. The device of claim 11 , further comprising another spacer formed on outer sidewalls of the seal spacer.
13. The device of claim 9 , wherein the second metal feature is adjacent the high k dielectric layer.
14. The device of claim 1 in which the second metal feature comprises titanium nitride with a nitrogen concentration different from a nitrogen concentration of the first metal feature.