Techniques for level shifting signals

1. A level shifter circuit comprising:

an input circuit operable to generate a pull-up signal in response to an input signal using charge from a supply voltage;

an inverter operable to invert the input signal to generate a pull-down signal, wherein the inverter comprises first and second complementary transistors operable to receive charge from the supply voltage;

a pull-up circuit operable to pull a level shifted output signal at an output terminal of the level shifter circuit to the supply voltage in response to the pull-up signal; and

a pull-down circuit operable to pull the level shifted output signal to a low voltage in response to the pull-down signal, wherein the pull-down circuit comprises a third transistor operable to receive the pull-down signal at a control input and a fourth cascode transistor coupled between the third transistor and the output terminal of the level shifter circuit, and wherein the fourth cascode transistor is operable to receive a first bias voltage at a control input that equals 50% or less of the supply voltage.

2. The level shifter circuit defined in claim 1 further comprising:

a source follower transistor operable to generate a reduced supply voltage from the supply voltage for supplying charge to the inverter.

3. The level shifter circuit defined in claim 1 , wherein the input circuit comprises:

a fifth transistor operable to receive the input signal at a control input;

a sixth cascode transistor coupled to the fifth transistor and operable to receive a second bias voltage at a control input;

a first resistor coupled to the sixth cascode transistor; and

a second resistor coupled to the first resistor, wherein the pull-up signal is generated between the first and the second resistors.

4. The level shifter circuit defined in claim 1 , wherein the pull-up circuit comprises a fifth transistor operable to receive the pull-up signal at a control input, and a sixth cascode transistor coupled to the fifth transistor, the sixth cascode transistor operable to receive a second bias voltage at a control input.

5. The level shifter circuit defined in claim 1 , wherein the level shifter circuit is fabricated on a programmable logic integrated circuit.

6. A level shifter circuit comprising:

an input circuit operable to generate a pull-up signal in response to an input signal using charge from a supply voltage;

an inverter operable to invert the input signal to generate a pull-down signal, wherein the inverter comprises first and second complementary transistors;

a pull-up circuit operable to pull a level shifted output signal of the level shifter circuit to the supply voltage in response to the pull-up signal;

a pull-down circuit operable to pull the level shifted output signal to a low voltage in response to the pull-down signal, wherein the pull-down circuit comprises a third transistor operable to receive the pull-down signal at a control input and a fourth cascode transistor coupled to the third transistor, and wherein the fourth cascode transistor is operable to receive a bias voltage at a control input; and

a source follower transistor operable to generate a reduced supply voltage from the supply voltage for supplying charge to the inverter,

wherein the source follower transistor is a thick-oxide transistor, the input circuit comprises thin-oxide transistors, the first and the second complementary transistors are thin-oxide transistors, the pull-up circuit comprises thin-oxide transistors, and the pull-down circuit comprises thin-oxide transistors.

7. A level shifter circuit comprising:

a first input circuit operable to generate a first pull-up signal in response to a first input signal using charge from a supply voltage;

a first inverter operable to invert the first input signal to generate a first pull-down signal, wherein the first inverter comprises first and second complementary transistors operable to receive charge from the supply voltage;

a first pull-up circuit operable to pull a first level shifted output signal of the level shifter circuit to the supply voltage in response to the first pull-up signal;

a first pull-down circuit operable to pull the first level shifted output signal to a low voltage in response to the first pull-down signal, wherein the first pull-down circuit comprises a third transistor operable to receive the first pull-down signal at a control input and a fourth cascode transistor coupled to the third transistor, and wherein the fourth cascode transistor is operable to receive a first bias voltage at a control input;

a second input circuit operable to generate a second pull-up signal in response to a second input signal using charge from the supply voltage;

a second inverter operable to invert the second input signal to generate a second pull-down signal, wherein the second inverter comprises fifth and sixth complementary transistors operable to receive charge from the supply voltage;

a second pull-up circuit operable to pull a second level shifted output signal of the level shifter circuit to the supply voltage in response to the second pull-up signal; and

a second pull-down circuit operable to pull the second level shifted output signal of the level shifter circuit to the low voltage in response to the second pull-down signal.

8. A level shifter circuit comprising:

an input circuit operable to generate a pull-up signal in response to an input signal using charge from a supply voltage;

a transistor operable to generate a reduced supply voltage using charge from the supply voltage;

a resistor divider operable to generate a bias voltage at a gate terminal of the transistor;

an inverter operable to invert the input signal to generate a pull-down signal using the reduced supply voltage from the transistor;

a pull-up circuit operable to pull a level shifted output signal of the level shifter circuit to the supply voltage in response to the pull-up signal; and

a pull-down circuit operable to pull the level shifted output signal of the level shifter circuit to a low voltage in response to the pull-down signal.

9. The level shifter circuit defined in claim 8 , wherein the inverter comprises complementary P-channel and N-channel transistors.

10. A level shifter circuit comprising:

an input circuit operable to generate a pull-up signal in response to an input signal using charge from a supply voltage, wherein the input circuit comprises a first resistor and a second resistor coupled to the first resistor, wherein the pull-up signal is generated between the first and the second resistors;

an inverter operable to invert the input signal to generate a pull-down signal using charge from the supply voltage;

a pull-up circuit operable to pull a level shifted output signal of the level shifter circuit to the supply voltage in response to the pull-up signal; and

a pull-down circuit operable to pull the level shifted output signal of the level shifter circuit to a low voltage in response to the pull-down signal.

11. The level shifter circuit defined in claim 10 , wherein the input circuit further comprises:

a first transistor operable to receive the input signal at a control input; and

a second cascode transistor coupled to the first transistor and operable to receive a bias voltage at a control input.

12. A level shifter circuit comprising:

an input circuit operable to generate a pull-up signal in response to an input signal using charge from a supply voltage, wherein the input circuit comprises a first transistor operable to receive the input signal at a control input, and a second cascode transistor coupled to the first transistor, and wherein the first transistor is coupled between a source of the second cascode transistor and a node at a ground voltage;

a third transistor operable to generate a reduced supply voltage using charge from the supply voltage;

a capacitor coupled to a control input of the third transistor;

an inverter operable to invert the input signal to generate a pull-down signal using the reduced supply voltage;

a pull-up circuit operable to pull a level shifted output signal at an output terminal of the level shifter circuit to the supply voltage in response to the pull-up signal; and

a pull-down circuit operable to pull the level shifted output signal to a low voltage in response to the pull-down signal.

13. The level shifter circuit defined in claim 12 further comprising:

a resistor divider coupled to the control input of the third transistor.

14. A level shifter circuit comprising:

a first input circuit operable to generate a first pull-up signal in response to a first input signal using charge from a supply voltage;

a source follower transistor operable to generate a reduced supply voltage using charge from the supply voltage;

a first inverter operable to invert the first input signal to generate a first pull-down signal using the reduced supply voltage from the source follower transistor;

a first pull-up circuit operable to pull a first level shifted output signal of the level shifter circuit to the supply voltage in response to the first pull-up signal;

a first pull-down circuit operable to pull the first level shifted output signal of the level shifter circuit to a low voltage in response to the first pull-down signal;

a second input circuit operable to generate a second pull-up signal in response to a second input signal using charge from the supply voltage;

a second inverter operable to invert the second input signal to generate a second pull-down signal using the reduced supply voltage from the source follower transistor;

a second pull-up circuit operable to pull a second level shifted output signal of the level shifter circuit to the supply voltage in response to the second pull-up signal; and

a second pull-down circuit operable to pull the second level shifted output signal of the level shifter circuit to the low voltage in response to the second pull-down signal.

15. The level shifter circuit defined in claim 14 , wherein the level shifter circuit is operable to transmit the first and the second level shifted output signals to a charge pump circuit in a clock data recovery circuit.

16. A method for level shifting an input signal to generate a level shifted output signal, the method comprising:

generating a pull-up signal in response to the input signal using a first transistor, a second cascode transistor, and charge from a supply voltage, wherein the input signal is provided to a control input of the first transistor, wherein a bias voltage is provided to a control input of the second cascode transistor, and wherein the first transistor is coupled between a source of the second cascode transistor and a node at a ground voltage;

generating a reduced supply voltage using a third transistor operable to provide charge from the supply voltage, wherein a control input of the third transistor is coupled to a capacitor;

inverting the input signal to generate a pull-down signal using the reduced supply voltage;

pulling the level shifted output signal to the supply voltage in response to the pull-up signal; and

pulling the level shifted output signal to a low voltage in response to the pull-down signal.

17. The method defined in claim 16 , wherein a resistor divider is coupled to the control input of the third transistor.

18. The method defined in claim 16 , wherein the third transistor is a source follower transistor.

19. The method defined in claim 16 , wherein inverting the input signal to generate the pull-down signal using the reduced supply voltage further comprises varying the pull-down signal between the reduced supply voltage and the low voltage, and wherein the reduced supply voltage is maintained at a substantially constant voltage.

20. A method for level shifting input signals to generate level shifted output signals, the method comprising:

generating a first pull-up signal in response to a first input signal using a first transistor, a second cascode transistor coupled to the first transistor, and charge from a supply voltage;

generating a reduced supply voltage using charge from the supply voltage;

inverting the first input signal to generate a first pull-down signal using the reduced supply voltage;

pulling a first level shifted output signal to the supply voltage in response to the first pull-up signal;

pulling the first level shifted output signal to a low voltage in response to the first pull-down signal;

generating a second pull-up signal in response to a second input signal using charge from the supply voltage;

inverting the second input signal to generate a second pull-down signal using the reduced supply voltage;

pulling a second level shifted output signal to the supply voltage in response to the second pull-up signal; and

pulling the second level shifted output signal to the low voltage in response to the second pull-down signal.

21. A method for level shifting an input signal to generate a level shifted output signal, the method comprising:

generating a pull-up signal in response to the input signal using a first transistor, a second cascode transistor coupled to the first transistor, and charge from a supply voltage;

generating a reduced supply voltage using charge from the supply voltage;

inverting the input signal to generate a pull-down signal using the reduced supply voltage;

pulling the level shifted output signal to the supply voltage in response to the pull-up signal; and

pulling the level shifted output signal to a low voltage in response to the pull-down signal, wherein generating the pull-up signal in response to the input signal using a first transistor, a second cascode transistor coupled to the first transistor, and charge from a supply voltage further comprises generating the pull-up signal between first and second resistors coupled to the second cascode transistor.