IP Library › Granted Patent US 8,034,690
Granted Patent B2
US 8,034,690 · App. 12/696,055 · Granted Oct 11, 2011

Method of etching oxide layer and nitride layer

Assignee: United Microelectronics Corp.
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Quick Facts
Patent No.
US 8,034,690
App. No.
12/696,055
Granted
Oct 11, 2011
Kind
B2
Abstract

An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are sequentially provided on the surface of the substrate, wherein the first oxide layer is uncovered on the isolating structure, the nitride layer is formed overlying the first oxide layer, and the second oxide layer is formed overlying the nitride layer. An isotropic etching process is performed by using an etching mask unmasking the isolating structure, and thereby removing the unmasked portion of the second oxide layer and the unmasked portion of the nitride layer and further exposing sidewalls of the isolating structure. The unmasked portion of the first oxide layer generally is partially removed due to over-etching.

Claims (14)

1. A method of etching an oxide layer and a nitride layer, comprising:

providing a substrate, wherein the substrate has an isolating structure;

providing a first oxide layer overlying the substrate while exposing the entire isolating structure;

providing a nitride layer overlying the first oxide layer as well as the isolating structure;

providing a second oxide layer overlying the nitride layer; and

performing an isotropic etching process by using an etching mask unmasking the isolating structure, and thereby removing an unmasked portion of the second oxide layer and an unmasked portion of the nitride layer, and further exposing sidewalls of the isolating structure.

2. The method as claimed in claim 1 , wherein the isotropic etching process further removes a part of the first oxide layer.

3. The method as claimed in claim 1 , further comprising: after the isotropic etching process, removing an unmasked portion of the first oxide layer by using the etching mask.

4. The method as claimed in claim 3 , further comprising: after removing the unmasked portion of the first oxide layer, removing the etching mask.

5. The method as claimed in claim 4 , further comprising: after removing the etching mask, forming a poly-silicon layer overlying the etched second oxide layer.

6. The method as claimed in claim 1 , wherein the etching mask is a patterned photoresist.

7. The method as claimed in claim 1 , wherein the substrate has an active region and an isolating region defined thereon, the isolating structure is disposed in the isolating region, and the etching mask is disposed in the active region.

8. The method as claimed in claim 1 , wherein the isotropic etching process is a dry etching process.

9. The method as claimed in claim 1 , wherein the isotropic etching process is a wet etching process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2010
From: SHIH, PING-CHIA; WANG, YU-CHENG; HUANG, CHUN-SUNG; YANG, YUAN-CHENG; HUANG, CHUNG-CHE; LIN, CHIN-FU
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 024208/0103 →
Continuity (1)
Related Publication 20110189859A1 · Aug 4, 2011