Simplified bias circuitry for differential buffer stage with symmetric loads

1. A delay locked loop comprising:

a delay line comprising a plurality of differential delay elements having V nbias inputs and V pbias inputs;

a biasing circuit comprising:

an input for receiving a control voltage, and a V nbias output for outputting a V nbias voltage for input to the V nbias inputs of the differential delay elements, and a V pbias output for outputting a V pbias voltage for input to the V pbias inputs of the differential delay elements;

a direct connection between the input and the V pbias output such that the V pbias output tracks the control voltage;

circuitry that produces the V nbias voltage from the control voltage, the circuitry comprising:

a pull-up network for pulling up the V nbias voltage when the control voltage is low;

a pull-down network for pulling down the V nbias voltage when the control voltage is high; and

a variable resistive element for impeding the pull-down network from pulling down the V nbias ;

wherein the pull-up network comprises a p-type transistor having a gate connected to receive the control voltage;

wherein the pull-down network comprises an n-type transistor having a gate connected to receive the control voltage.

2. The delay locked loop of claim 1 wherein:

each differential delay element comprises:

an input differential pair of transistors that receive a differential input, sources of the input differential pair connected to a drain of another transistor, the V nbias voltage connected to a gate of the another transistor;

a first symmetric load element and a second symmetric load element, the first and second symmetric load elements connected to the input differential pair of transistors, and also connected to receive the V pbias voltage.

3. The delay locked loop of claim 2 wherein the input differential pair of transistors comprises:

a first n-type transistor having a gate connected to receive a first end of the differential input, a source connected to a drain of the another transistor, and a drain connected to the first symmetric load element;

a second n-type transistor having a gate connected to receive a second end of the differential input, a source connected to the drain of the another transistor, and a drain connected to the second symmetric load element.

4. The delay locked loop of claim 3 wherein the another transistor has a source connected to a first supply.

5. The delay locked loop of claim 2 wherein:

the first symmetric load element comprises:

a first p-type transistor and a second p-type transistor connected to form a differential pair of transistors;

the first p-type transistor having a source, gate, and drain,

the second p-type transistor having a source, gate, and drain,

the drains of the first and second p-type transistors connected together and to the gate of the first p-type transistor;

the sources of the first and second p-type transistors connected together and to a second supply voltage; and

the gate of the second p-type transistor connected to receive the V nbias voltage;

wherein the second symmetric load element comprises:

a first p-type transistor and a second p-type transistor connected to form a differential pair of transistors;

the first p-type transistor having a source, gate, and drain,

the second p-type transistor having a source, gate, and drain,

the drains of the first and second p-type transistors connected together and to the gate of the first p-type transistor;

the sources of the first and second p-type transistors connected together and to the second supply voltage; and

the gate of the second p-type transistor connected to receive the V nbias voltage.

6. The delay locked loop of claim 1 wherein the variable resistor comprises a diode connected transistor between the p-type transistor and the n-type transistor, the V nbias voltage being output at a drain of the p-type transistor.

7. A delay locked loop comprising:

a delay line comprising a plurality of differential delay elements having V nbias inputs and V pbias inputs;

a biasing circuit comprising:

an input for receiving a control voltage, and a V nbias output for outputting a V nbias voltage for input to the V nbias inputs of the differential delay elements, and a V pbias output for outputting a V pbias voltage for input to the V pbias inputs of the differential delay elements;

a direct connection between the input and the V pbias output such that the V pbias output tracks the control voltage:

circuitry that produces the V nbias voltage from the control voltage, the circuitry comprising:

a pull-up network for pulling up the V nbias voltage when the control voltage is low;

a pull-down network for pulling down the V nbias voltage when the control voltage is high; and

a variable resistive element for impeding the pull-down network from pulling down the V nbias ;

wherein the circuitry that produces the V nbias voltage from the control voltage does so such that the V nbias voltage is near a supply voltage V DD over a first control voltage range, sharply declines over a second control voltage range that follows the first control voltage range, and less sharply declines in a substantially linear manner over a third control voltage range that follows the second control voltage range.

8. The delay locked loop of claim 7 wherein the first voltage range is from about 0.0V to about 0.2V, the second voltage range is from about 0.2V to about 0.4V, and the third voltage range is a range above about 0.4V.

9. The delay locked loop of claim 7 wherein each of the voltage ranges is a respective range between 0 and V DD .

10. The delay locked loop of claim 1 comprising:

a reference clock input to a first of the differential delay elements, a last of the differential delay elements outputting a delayed clock;

a phase detector connected to receive the input clock and the delayed clock and to produce at least one control signal as a function of a phase detected;

a charge pump connected to receive the at least one control signal and connected to output the control voltage to the biasing circuit.