Maintenance process to enhance memory endurance
View Patent ↗Subject matter disclosed herein relates to enhancing an operational lifespan of non-volatile memory.
1. A method comprising:
operating a non-volatile phase change memory device in a storage mode with a write pulse comprising a first current amplitude and a first duration;
partitioning said non-volatile memory device into at least a first portion and a second portion;
applying a memory cell maintenance process to said first portion to operate said first portion with a maintenance pulse, wherein said maintenance pulse comprises a polarity that is the same as a polarity of said write pulse; and
returning said first portion to operate in said storage mode.
2. The method of claim 1 , wherein applying said memory cell maintenance process further comprises:
applying said maintenance pulse to one or more memory cells of said first portion, wherein said maintenance pulse comprises a second current amplitude that is greater than or equal to said first current amplitude and/or a second duration that is greater than or equal to said first duration.
3. The method of claim 1 , further comprising:
subsequent to returning said first portion to operate in said storage mode, applying said memory cell maintenance process to said second portion to operate said second portion with said maintenance pulse; and
returning said second portion to operate in said storage mode.
4. The method of claim 1 , wherein said non-volatile memory device comprises a phase change memory (PCM) that includes a phase-change material.
5. The method of claim 4 , wherein said maintenance pulse is sufficient to melt said phase-change material.
6. The method of claim 5 , wherein said phase-change material comprises germanium antimony telluride (GST).
7. The method of claim 1 , further comprising:
before applying said memory cell maintenance process to said first portion, copying information stored in said first portion to a third portion of said non-volatile memory device, wherein said applying said memory cell maintenance process to said first portion results in said first portion being erased.
8. The method of claim 7 , further comprising:
after applying said memory cell maintenance process to said first portion, copying said information stored in said third portion to said first portion of said non-volatile memory device.
9. The method of claim 7 , further comprising:
applying said memory cell maintenance process to said first portion in response to detecting one or more bit errors from said first portion.
10. A non-volatile phase change memory device comprising:
a memory cell array; and
a controller to:
operate said memory cell array in a storage mode with a write pulse comprising a first current amplitude and a first duration;
partition said memory cell array into at least a first portion and a second portion;
apply a memory cell maintenance process to said first portion to operate said first portion with a maintenance pulse, wherein said maintenance pulse comprises a polarity that is the same as a polarity of said write pulse; and
return said first portion to operate in said storage mode.
11. The non-volatile memory device of claim 10 , wherein said memory cell maintenance process comprises said maintenance pulse applied to one or more memory cells of said first portion, wherein said maintenance pulse comprises a second current amplitude that is greater than or equal to said first current amplitude and/or a second duration that is greater than or equal to said first duration.
12. The non-volatile memory device of claim 10 , wherein said controller is adapted to:
apply said memory cell maintenance process to said second portion subsequent to returning said first portion to operate in said storage mode; and
return said second portion to operate in said storage mode.
13. The non-volatile memory device of claim 10 , further comprising a phase change memory (PCM) that includes a phase-change material.
14. The non-volatile memory device of claim 13 , wherein said maintenance pulse is sufficient to melt said phase-change material.
15. The non-volatile memory device of claim 14 , wherein said phase-change material comprises germanium antimony telluride (GST).
16. A system comprising:
a non-volatile phase change memory device writeable by a pulse comprising a first current amplitude and a first duration;
a controller to apply a memory cell maintenance process to a portion of said non-volatile memory device by supplying said portion of said non-volatile memory device with a maintenance pulse, wherein said maintenance pulse comprises a polarity that is the same as a polarity of said pulse, and wherein said maintenance pulse comprises a second current amplitude and/or a second current duration greater than or equal to said first current amplitude and/or first current duration, respectively; and
a processor to host one or more applications to initiate commands to said controller to store information in and/or retrieve information from said non-volatile memory device.
17. The system of claim 16 , wherein said controller is adapted to partition said non-volatile memory device to a first portion subject to said memory cell maintenance process and a second portion to store memory contents of said first portion while said first portion is subject to said memory cell maintenance process.
18. The system of claim 17 , wherein said controller is adapted to:
apply said memory cell maintenance process to said second portion to operate said second portion with said maintenance pulse.
19. The system of claim 16 , wherein said non-volatile memory device comprises a phase change memory (PCM) that includes a phase-change material.
20. The system of claim 19 , wherein said maintenance pulse is sufficient to melt said phase-change material.