IP Library Granted Patent US 8,037,118
Granted Patent B2
US 8,037,118 · App. 12/082,127 · Granted Oct 11, 2011

Three-path fused multiply-adder circuit

Assignee: Eric Quinnell
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Quick Facts
Patent No.
US 8,037,118
App. No.
12/082,127
Granted
Oct 11, 2011
Kind
B2
Abstract

A three-path floating-point fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The three-path fused multiply-adder is based on a dual-path adder and reduces latency significantly by operating on case data in parallel and by reducing component bit size. The fused multiply-adder is a common serial fused multiply-adder that reuses floating-point adder (FPA) and floating-point multiplier (FPM) hardware, allowing single adds, single multiplies, and fused multiply-adds to execute at maximum speed.

Claims (6)

1. A fused multiply-adder circuit comprising:

a multiplier for multiplying a first operand and a second operand to generate a product;

an adder anchor path for shifting said product with respect to a third operand;

a product anchor path for shifting said third operand with respect to said product;

a close path for normalizing a difference between said product and said third operand; and

an add/round module for selecting and finishing an output from one of said paths to generate a result.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2014
From: QUINNELL, ERIC CHARLES
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 033825/0689 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2014
From: BOARD OF REGENTS OF THE UNIVERSITY OF TEXAS SYSTEM; SWARTZLANDER, EARL, JR; LEMONDS, CARL
To: QUINNELL, ERIC
Reel/Frame 032824/0985 →
Continuity (2)
Provisional Application 60911018 · Apr 10, 2007
Related Publication 20080256150A1 · Oct 16, 2008