Apparatus and method for synchronizing a channel card in a mobile communication system

1. A channel card for synchronizing a Digital Signal Processing (DSP) modem and a system clock in a mobile communication system, comprising:

the DSP modem for sending a reference signal, informing of a start of a transmission, to a Field-Programmable Gate Array (FPGA) modem; and

the FPGA modem for comparing a reception time of the reference signal with a Global Positioning System (GPS) timer, for recording a GPS timer value corresponding to a start point based on the comparison, and for sending to the DSP modem the recorded GPS timer value corresponding to the start point at a preset GPS timer reference time,

wherein the FPGA modem comprises a GPS timer for receiving system clock information from a GPS part and for recording the GPS timer value corresponding to a start point at the reception time of the reference signal, and for sending the GPS timer value corresponding to the start point to the DSP modem at the preset GPS timer reference time, and

wherein the I/O matching part delays the traffic data output from the DSP modem by one sample writing time of a Dual-Port Random Access Memory (DPRAM) and then outputs the traffic data from the DPRAM.

2. The channel card of claim 1 , wherein the DSP modem adjusts start point information by referring to the GPS timer value.

3. The channel card of claim 2 , wherein the DSP modem sends traffic data to the FPGA modem together with the adjusted start point information.

4. The channel card of claim 1 , wherein the FPGA modem further comprises:

an Input/Output (I/O) matching part for receiving traffic data and the reference signal from the DSP modem, for sending the reference signal to the GPS timer, and for formatting the traffic data according to a Multi-Gigabit Transceiver (MGT) format.

5. The channel card of claim 4 , wherein the FPGA modem further comprises:

a MGT matching part for converting parallel data output from the I/O matching part using a serial Low Voltage Differential Signaling (LVDS) format, for matching the converted data with an InterFace (IF) board, for converting UL serial LVDS input data into parallel data, and for sending the converted parallel data to the I/O matching part.

6. The channel card of claim 1 , wherein a data format for data sent from the DSP modem to the FPGA modem comprises 16-bit parallel data and a 1-bit sync signal, and comprises start information.

7. The channel card of claim 1 , wherein a data format for data sent from the FPGA modem to the DSP modem comprises 16-bit parallel data and a 1-bit sync signal, and comprises GPS time based start information.

8. A method for synchronizing a system clock in a Digital Signal Processing (DSP) modem of a channel card, the method comprising:

sending a reference signal, informing of a data transmission start point, from the DSP modem to a Field-Programmable Gate Array (FPGA) modem;

comparing, by the FPGA modem, a reception time point of the sent reference signal with a Global Positioning System (GPS) timer;

recording, by the FPGA modem, a GPS timer value based on the comparison;

sending, by the FPGA modem, the recorded GPS timer value, at a preset GPS timer reference time, to the DSP modem;

adjusting, by the DSP modem, start point information by referring to the GPS timer value; and

sending, by the DSP modem, traffic data to the FPGA modem together with the adjusted start point information,

wherein the FPGA modem delays the traffic data by one sample writing time of a Dual-Port Random Access Memory (DPRAM) and then outputs the traffic data from the DPRAM.

9. The method of claim 8 , wherein the start point information comprises certain bit information of a time information frame.

10. The method of claim 9 , wherein the certain bit information comprises four bits.

11. The method of claim 8 , wherein the GPS timer value comprises a frame sync timer count value and a symbol sync timer count value.

12. The method of claim 8 , further comprising:

receiving the start point information and traffic data;

sending the start point information to the GPS timer; and

formatting the traffic data according to a Multi-Gigabit Transceiver (MGT) format.

13. The method of claim 12 , wherein the traffic data comprises parallel data and is converted into a serial Low Voltage Differential Signal (LVDS) format and matched with an InterFace (IF) board.

14. The method of claim 8 , wherein a data format for data sent from the DSP modem to the FPGA modem comprises 16-bit parallel data and a 1-bit sync signal, and comprises start information.

15. The method of claim 8 , wherein a data format for data sent from the FPGA modem to the DSP modem comprises 16-bit parallel data and a 1-bit sync signal, and comprises GPS time based start information and UL start point information.

16. A method for synchronizing a plurality of channel cards in a Field-Programmable Gate Array (FPGA) modem of each of the plurality of channel cards, the method comprising:

receiving traffic data from a Digital Signal Processing (DSP) modem;

writing the received traffic data to a Dual-Port Random Access Memory (DPRAM); and

reading the traffic data from the DPRAM after a time delay,

wherein the time delay comprises an amount of time substantially equal to one sample writing time of the DPRAM.

17. A channel card for synchronizing a first modem and a system clock in a mobile communication system, comprising:

the first modem for sending a reference signal, informing of a transmission start point, to a second modem; and

the second modem for comparing a reception time of the reference signal with a Global Positioning System (GPS) timer, for recording a GPS timer value corresponding to a start point based on the comparison, and for sending to the first modem the recorded GPS timer value corresponding to the start point at a preset GPS timer reference time,

wherein the second modem delays traffic data output from the first modem by on sample writing time of a Dual-Port Random Access Memory (DPRAM) and then outputs the traffic data from the DPRAM.