Gating circuitry coupling selected scan paths between I/O scan bus
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.
1. A semiconductor integrated circuit comprising;
A. a substrate of semiconductor material;
B. functional logic formed on the substrate, the functional logic including functional flip-flops;
C. scan paths formed on the substrate, each scan path including a scan input bus for receiving test stimulus data to be applied to the functional logic, connections with the functional logic for applying stimulus data to the functional logic and receiving response data from the functional logic, a scan output bus for transmitting test response data obtained from the functional logic, and a control bus input for operating the parallel scan paths, each scan path including functional flip-flops of the functional logic that, in a test mode, are connected in series: and
D. gating circuitry connected to the scan input bus, the scan paths, and the scan output bus, the gating circuitry having an enable input, and the gating circuitry in response to receiving one enable signal coupling the scan paths in series between the scan input bus and the scan output bus and in response to receiving another enable signal selectively coupling only one of the scan paths between the scan input bus and the scan output bus.
2. The integrated circuit claim 1 including control leads connected to the scan paths, the control leads carrying signals for shifting stimulus data from the scan input bus on the scan paths, applying stimulus data from the scan paths to the functional logic, capturing response data from the functional logic in the scan paths, and shifting response data on the scan paths to the output bus.
3. The integrated circuit of claim 1 in which the one enable signal is an enable signal of one state on the enable input and the another enable signal is an enable signal of another state on the enable input.
4. The integrated circuit of claim 1 including comparator circuitry having an expected data input, a mask data input, an input coupled to the scan output bus of each scan path, and a fail flag output.
5. The integrated circuit of claim 1 in which the functional logic is combinational logic.
6. The integrated circuit of claim 1 in which the gating circuitry includes multiplexers coupling the scan paths together.