IP Library Granted Patent US 8,037,448
Granted Patent B2
US 8,037,448 · App. 12/122,307 · Granted Oct 11, 2011

Language and templates for use in the design of semiconductor products

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Quick Facts
Patent No.
US 8,037,448
App. No.
12/122,307
Granted
Oct 11, 2011
Kind
B2
Abstract

During the design of semiconductor products which incorporates a user specification and an application set, the application set being a partially manufactured semiconductor platform and its resources, a template engine is disclosed which uses a simplified computer language having a character whereby data used in commands identified by the character need only be input once, either by a user or by files, and that data, after it has been verified to be correct, is automatically allocated to one or more templates used to generate shells for the specification of a final semiconductor product. Data must be correct and compatible with other data before it can be used within the template engine and the generated shells; indeed the template engine cooperates with a plurality of rules and directives to verify the correctness of the data. The template engine may generate one or more of the following shells: an RTL shell, a documentation shell, a timing analysis shell, a synthesis shell, a manufacturing test shell, and/or a floorplan shell.

Claims (27)

1. A template engine, at least partially stored on a computer-readable memory and comprising:

(a) means to read a plurality of resources available from a selected application set;

(b) means to input a user's specification; and

(c) means to generate a plurality of shells allocating the resources of the application set to the user's specification, the plurality of shells comprising at least two from a group comprising a Register Transfer Level shell providing a logical description, a documentation shell providing a functional description, and a timing analysis shell providing a timing description.

2. The template engine of claim 1 , wherein the user's specification further comprises additional resources for allocation to the specification.

3. The template engine of claim 2 , wherein the user's specification and the resources are in a specific language and format for use with the template engine.

4. The template engine of claim 3 , wherein the specific language cooperates with other hardware description languages, and comprises block commands and simple commands, the commands having a character indicating its use in the template engine.

5. The template engine of claim 4 wherein the plurality of shells further comprise at least one shell each of a Register Transfer Level shell providing a logical description, a documentation shell providing a functional description, a verification shell providing a functional verification description, a synthesis shell providing a generation description, a static timing shell providing a timing description, a manufacturing test shell providing a test description, and a floor plan shell providing a location description.

6. The template engine of claim 5 wherein a same block command is usable to form each shell.

7. The template engine of claim 1 , wherein the allocation of the resources to the user's specification are verified before generation of the shells.

8. The template engine of claim 1 , further comprising means to display the resources and parameters affecting allocation.

9. The template engine of claim 8 , further comprising means to allow a user to interact to select and allocate resources to the user's specification.

10. The template engine of claim 1 wherein the documentation shell comprises a documentation shell written in a markup language.

11. A method to generate shells, comprising the steps of:

(a) storing a plurality of parameters derived from a user's specification and an application set;

(b) receiving a selection of a shell to generate;

(c) invoking a template of the shell, the template of the shell comprising a block command to repeat a block of text;

(d) reading the parameters used in the template;

(e) a processor exploding the template with the called parameters to form a shell such that the block of text is repeated in the shell; and

(f)making the shell available to a user.

12. A template engine by which to generate at least one shell and specification of a semiconductor platform, the template engine at least partially stored on a computer-readable memory and comprising:

(a) a language by which to enter parameters derived from a user and from an application set into the template engine, the language having a character to indicate insertion of parameters into at least two shells, each shell having a different format;

(b) at least one template pertaining to the at least one shell;

(c) a verifier to verify that a considered parameter is correct and compatible with other parameters prior to allocation of the considered parameter to the at least one shell and specification of the semiconductor platform;

(d) an allocator which allocates the considered parameter to the at least one shell and the specification of the semiconductor platform; and

(e) a shell generator responsive to the allocator and the user whereby a user can generate at least two shells having two different formats wherein one of the shells has a markup language format for the semiconductor product.

13. The template engine of claim 12 , wherein the template engine is embodied in a computer program product.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →