Supply regulated charge pump system

1. An apparatus, comprising:

a charge pump circuit;

a clock driver coupled with the charge pump circuit, wherein the clock driver is configured to provide a regulated clock signal having a constant frequency to the charge pump circuit; and

a voltage regulator coupled with the charge pump circuit, the voltage regulator comprising:

an amplifier configured to provide an output voltage of the amplifier corresponding to a difference between a reference voltage and a voltage that is proportional to the output voltage of the charge pump circuit; and

a transistor, wherein a gate of the transistor is coupled with the output voltage of the amplifier, a source of the transistor is coupled with a voltage source, and a drain of the transistor is configured to provide the regulated supply voltage, the voltage regulator configured to maintain an output voltage of the charge pump circuit near a target voltage by applying a regulated supply voltage to a voltage input of the charge pump circuit and to a voltage input of the clock driver, wherein the voltage regulator adjusts the regulated supply voltage in response to the output voltage of the charge pump circuit, the regulated supply voltage to increase when the output voltage of the charge pump circuit decreases and the regulated supply voltage to decrease when the output voltage of the charge pump circuit increases, wherein the constant frequency of the regulated clock signal is independent from the output voltage of the charge pump circuit.

2. The apparatus of claim 1 , wherein the voltage regulator is a low drop-out (LDO) regulator.

3. The apparatus of claim 1 , further comprising a voltage divider coupled with a voltage output of the charge pump circuit, wherein the voltage divider is configured to produce a divided output voltage from the output voltage of the charge pump circuit, and wherein the voltage regulator adjusts the regulated supply voltage in response to the output voltage of the charge pump circuit by comparing a reference voltage with the divided output voltage.

4. The apparatus of claim 1 , wherein the clock driver is configured to adjust an amplitude of the regulated clock signal based on the regulated supply voltage.

5. The apparatus of claim 1 , wherein the clock driver is configured to receive a reference clock signal that determines a frequency and a duty cycle of the regulated clock signal.

6. The apparatus of claim 1 , wherein the clock driver comprises pulse logic configured to produce the regulated clock signal and an inverted clock signal, wherein pulses of the inverted clock signal are non-overlapping with respect to pulses of the regulated clock signal.

7. The apparatus of claim 1 , wherein the charge pump circuit includes a plurality of charge pump cells, wherein one of the plurality of charge pump cells boosts an output voltage of another of the plurality of charge pump cells, and wherein the clock driver provides the regulated clock signal to each of the plurality of charge pump cells.

8. The apparatus of claim 1 , wherein the output voltage of the charge pump circuit is a positive voltage, an output to input voltage ratio is greater than approximately 4:1, and wherein a total area occupied by the charge pump circuit, the voltage regulator, and the clock driver is less than about 40,000 square microns.

9. The apparatus of claim 1 , wherein the output voltage of the charge pump circuit is a negative voltage, an output to input voltage ratio is greater than approximately 2.5:1, and wherein a total area occupied by the charge pump circuit, the voltage regulator, and the clock driver is less than about 60,000 square microns.

10. A method, comprising:

adjusting a regulated supply voltage based on an output voltage of a charge pump circuit;

generating a regulated clock signal having a constant frequency; and

maintaining the output voltage of the charge pump circuit near a target voltage by applying the regulated supply voltage to a voltage input of the charge pump circuit while applying the regulated clock signal to a clock input of the charge pump circuit, wherein the adjusting the regulated supply voltage comprises:

comparing the output voltage of the charge pump circuit with a reference voltage; and

controlling a transistor based on a difference between the output voltage of the charge pump circuit and the reference voltage, wherein the regulated supply voltage increases when the output voltage of the charge pump circuit decreases and the regulated supply voltage decreases when the output voltage of the charge pump circuit increases, wherein the constant frequency of the regulated clock signal is independent from the output voltage of the charge pump circuit.

11. The method of claim 10 , wherein comparing the output voltage of the charge pump circuit with the reference voltage comprises dividing the output voltage of the charge pump circuit.

12. The method of claim 10 , further comprising adjusting an amplitude of the regulated clock signal in response to changes in the regulated supply voltage.

13. The method of claim 10 , further comprising receiving a reference clock signal to determine a frequency and a duty cycle of the regulated clock signal.

14. The method of claim 10 , further comprising:

generating an inverted clock signal, wherein pulses of the inverted clock signal are non-overlapping with respect to pulses of the regulated clock signal; and

applying the inverted clock signal to the charge pump circuit.

15. The method of claim 10 , wherein the output voltage of the charge pump circuit has a ripple voltage less than about 50 millivolts.

16. The method of claim 10 , wherein a ripple voltage frequency of the output voltage is independent of a load current supplied by the charge pump circuit.