Degradation correction for finFET circuits
A pair of split-gate fin field effect transistors (finFETs) in an IC, each containing a signal gate and a control gate, in which an adjustable voltage source, preferably in the form of a digital-to-analog-converter (DAC), is connected to the control gate of one of the finFETs, is disclosed. Threshold measurement circuits on the signal gates enable a threshold adjustment voltage from the adjustable voltage source to reduce the threshold mismatch between the finFETs. Adding a second DAC to the second finFET allows a simpler DAC design. Threshold correction may be performed during the operational life of the IC. Implementations in a differential input stage of an amplifier and in a current mirror circuit are described.
1. A pair of split-gate fin field effect transistors (finFETs), comprising:
a first finFET, further comprising a first control gate laterally abutting a first transistor body region through a first control gate dielectric layer, laterally opposite a first signal gate;
a second finFET, further comprising a second control gate laterally abutting a second transistor body region through a second control gate dielectric layer, laterally opposite a second signal gate; and
an adjustable voltage source which is electrically connected to said first control gate.
2. The pair of split-gate finFETs of claim 1 , in which said adjustable voltage source is a digital-to-analog-converter (DAC).
3. The pair of split-gate finFETs of claim 2 , in which a reference node of said DAC is connected to a first drain node of said first finFET.
4. The pair of split-gate finFETs of claim 2 , in which a reference node of said DAC is connected to a constant voltage power supply node.
5. The pair of split-gate finFETs of claim 2 , further comprising a second DAC which is connected to said second control gate.
6. The pair of split-gate finFETs of claim 5 , in which:
a first reference node of said first DAC is connected to a first drain node of said first finFET; and
a second reference node of said second DAC is connected to a second drain node of said second finFET.
7. The pair of split-gate finFETs of claim 5 , in which:
a first reference node of said first DAC is connected to a constant voltage power supply node; and
a second reference node of said second DAC is connected to said constant voltage power supply node.
8. An integrated circuit, comprising:
a pair of split-gate finFETs, further comprising:
a first finFET, further comprising a first control gate laterally abutting a first transistor body region through a first control gate dielectric layer, laterally opposite a first signal gate;
a second finFET, further comprising a second control gate laterally abutting a second transistor body region through a second control gate dielectric layer, laterally opposite a second signal gate; and
an adjustable voltage source which is electrically connected to said first control gate;
a first threshold measurement circuit connected to said first signal gate of said first finFET; and
a second threshold measurement circuit connected to said second signal gate of said second finFET.
9. The integrated circuit of claim 8 , in which said adjustable voltage source is a digital-to-analog-converter (DAC).
10. The integrated circuit of claim 9 , in which a reference node of said DAC is connected to a first drain node of said first finFET.
11. The integrated circuit of claim 9 , in which a reference node of said DAC is connected to a constant voltage power supply node.
12. The integrated circuit of claim 9 , further comprising a second DAC which is connected to said second control gate.
13. The integrated circuit of claim 12 , in which:
a first reference node of said first DAC is connected to a first drain node of said first finFET; and
a second reference node of said second first DAC is connected to a second drain node of said second finFET.
14. The integrated circuit of claim 12 , in which:
a first reference node of said first DAC is connected to a constant voltage power supply node; and
a second reference node of said second DAC is connected to said constant voltage power supply node.
15. The integrated circuit of claim 8 , further comprising differential input amplifier circuitry connected to a first source node of said first finFET and connected to a second source node of said second finFET, which produces an output signal proportional to a difference of an input potential on said first signal gate and an input potential on said second signal gate.
16. The integrated circuit of claim 8 , further comprising:
a current source connected to a first drain node of said first finFET;
a direct electrical connection between said first signal gate and said first drain node; and
a direct electrical connection between said first signal gate and said second signal gate.
17. A method of operating an integrated circuit, comprising the steps of:
forming a pair of split-gate finFETs in said integrated circuit, by a process further comprising the steps of:
forming a first finFET, by a process further comprising the step of forming a first control gate laterally abutting a first transistor body region through a first control gate dielectric layer, laterally opposite a first signal gate;
forming a second finFET, by a process further comprising the step of forming a second control gate laterally abutting a second transistor body region through a second control gate dielectric layer, laterally opposite a second signal gate; and
forming an adjustable voltage source such that said adjustable voltage source is electrically connected to said first control gate;
forming a first threshold measurement circuit such that said first threshold measurement circuit is connected to said first signal gate of said first finFET;
forming a second threshold measurement circuit such that said second threshold measurement circuit is connected to said second signal gate of said second finFET;
performing a first measurement of a first threshold voltage of said first finFET with respect to said first signal gate by a process comprising operation of said first threshold measurement circuit;
performing a second measurement of a second threshold voltage of said second first finFET with respect to said second signal gate by a process comprising operation of said second threshold measurement circuit; and
providing a threshold adjustment voltage from said adjustable voltage source such that said first threshold voltage matches said second threshold voltage within 1 millivolt.
18. The method of claim 17 , further comprising the steps of:
performing a third measurement of said first threshold voltage of said first finFET with respect to said first signal gate by a process comprising operation of said first threshold measurement circuit;
performing a fourth measurement of said second threshold voltage of said second finFET with respect to said second signal gate by a process comprising operation of said second threshold measurement circuit; and
providing a second threshold adjustment voltage from said adjustable voltage source such that said first threshold voltage matches said second threshold voltage within 1 millivolt.
19. The method of claim 17 , further comprising the steps of:
forming a second adjustable voltage source such that said second adjustable voltage source is electrically connected to said second control gate;
performing a third measurement of said first threshold voltage of said first finFET with respect to said first signal gate by a process comprising operation of said first threshold measurement circuit;
performing a fourth measurement of said second threshold voltage of said second finFET with respect to said second signal gate by a process comprising operation of said second threshold measurement circuit; and
providing a second threshold adjustment voltage from said second adjustable voltage source such that said first threshold voltage matches said second threshold voltage within 1 millivolt.