IP Library Granted Patent US 8,060,324
Granted Patent B2
US 8,060,324 · App. 12/162,179 · Granted Nov 15, 2011

Device and a method for estimating transistor parameter variations

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Quick Facts
Patent No.
US 8,060,324
App. No.
12/162,179
Granted
Nov 15, 2011
Kind
B2
Abstract

A method and a device for estimating parameter variations of transistors that belong to the same circuit. The method includes: providing the first circuit; providing a test circuit adapted to perform a first function and a stacked test circuit adapted to perform a second function that substantially equals the first function; wherein the test circuit, the stacked test circuit and the first circuit are processed under substantially the same processing conditions; determining a relationship between a parameter of the test circuit and a parameter of the stacked test circuit; and estimating parameter variations of transistors that belong to the first circuit in response to the determined relationship.

Claims (38)

1. A method for estimating parameter variations of transistors that belong to a first circuit, the method comprises:

providing the first circuit;

providing a test circuit adapted to perform a first function and a stacked test circuit adapted to perform a second function that substantially equals the first function wherein the first circuit, the test circuit, and the stacked test circuit are different circuits;

wherein the test circuit, the stacked test circuit and the first circuit are processed under substantially the same processing conditions;

determining a relationship between a parameter of the test circuit and a parameter of the stacked test circuit, wherein the parameter of the test circuit is a same type of parameter as the parameter of the stacked test circuit; and

estimating parameter variations of transistors that belong to the first circuit in response to the determined relationship; wherein the determining comprises searching for a supply voltage range that when supplied to the first circuit will result in parameter variation difference level that does not exceed an acceptable parameter variation difference.

2. The method according to claim 1 wherein the providing is preceded by manufacturing the first circuit, test circuit and stacked test circuit on a single die.

3. The method according to claim 1 wherein the determining comprises measuring the parameter of the stacked test circuit, measuring the parameter of the test circuit and calculating a relationship between the parameter of the test circuit and the parameter of the stacked test circuit.

4. The method according to claim 1 wherein the determining comprises:

supplying a supply voltage level to the stacked test circuit and to the test circuit;

calculating a relationship between the parameter of the test circuit and the parameter of the stacked test circuit; and

altering the supply voltage level and jumping to calculating the relationship.

5. The method according to claim 1 wherein the method further comprises defining the acceptable parameter variation difference.

6. The method according to claim 5 wherein the method comprises supplying to the first circuit a supply voltage; wherein the supply voltage has a level within the supply voltage range.

7. The method according to claim 5 wherein the method comprises supplying to the first circuit a supply voltage having a level that is substantially a lowest level in the supply voltage range.

8. The method according to claim 1 wherein the method comprises repetitively performing the stages of determining, estimating and supplying to the first circuit a supply voltage, wherein the supply voltage is responsive to the estimation.

9. The method according to claim 1 wherein the parameter is a delay.

10. The method according to any claim 1 wherein the parameter is a leakage current.

11. A device having parameter variations estimation capabilities, the device comprises:

a first circuit;

a controller, and a test unit that comprises a test circuit adapted to perform a first function and stacked test circuit adapted to perform a second function that substantially equals the first function, wherein the first circuit, the test circuit, and the stacked test circuit are different circuits;

wherein the test circuit, the stacked test circuit and the first circuit are processed under substantially the same processing conditions;

wherein the controller is adapted to determine a relationship between a parameter of the test circuit and a parameter of the stacked test circuit, to estimate parameter variations of transistors that belong to the first circuit in response to the determined relationship, and to search for a supply voltage range that when supplied to the first circuit will result in parameter variation difference level that does not exceed an acceptable parameter variation difference, wherein the parameter of the test circuit is a same type of parameter as the parameter of the stacked test circuit.

12. The device according to claim 11 wherein the first circuit, the test circuit and the stacked test circuit are manufactured on a single die.

13. The device according to claim of claims 11 wherein the controller is adapted to measure the parameter of the stacked test circuit, measure the parameter of the test circuit and compare between the measured parameters.

14. The device according to claim 11 wherein the controller is adapted to control a test supply unit to supply a first supply voltage level to the test circuit and to the stacked test circuit; to calculate a relationship between the parameter of the test circuit and the parameter of the stacked test circuit, to control an alteration of the supply voltage level and to re-calculate the relationship.

15. The device according to claim 11 wherein the device is adapted to calculate the acceptable parameter variation difference.

16. The device according to claim 15 wherein the controller is adapted to control a first supply unit adapted to provide to the first circuit a supply voltage; wherein the supply voltage has a level that is within the supply voltage range.

17. The device according to claim 15 wherein the controller is adapted to control a first supply unit adapted to provide to the first circuit a supply voltage that is substantially a lowest level in the supply voltage range.

18. The device according to claim 11 wherein the controller is adapted to repetitively determine, estimate and control a supply of voltage to the first circuit; wherein the supply voltage is responsive to the estimation.

19. The device according to claim 11 wherein the parameter is a delay.

20. A method for estimating parameter variations of transistors that belong to a first circuit, the method comprises:

providing the first circuit;

providing a test circuit and a stacked test circuit, wherein the test circuit, the stacked test circuit and the first circuit are processed under substantially the same processing conditions, and wherein the first circuit, the test circuit, and the stacked test circuit are different circuits;

measuring a parameter of the test circuit and a parameter of the stacked test circuit at a plurality of supply voltage levels, wherein the parameter of the test circuit is a same type of parameter as the parameter of the stacked test circuit;

comparing the parameter of the test circuit with the parameter of the stacked test circuit at each of the plurality of supply voltage levels to determine a parameter variation difference level between the parameter of the test circuit and the parameter of the stacked test circuit at each of the supply voltage levels;

estimating parameter variations of transistors that belong to the first circuit in response to the difference between the parameter of the test circuit and the parameter of the stacked test circuit; and

determining a supply voltage level of the plurality of supply voltage levels that when supplied to the first circuit will result in the parameter variation difference level that does not exceed an acceptable parameter variation difference.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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