Phase interpolator for a timing signal generating circuit
A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
1. A phase interpolator comprising:
an analog periodic waveform generator for generating analog periodic waveforms whose value varies in analog fashion, from a digital periodic signal whose amplitude represents a digital value;
a weighting control circuit for controlling the weighting of each of said analog periodic waveforms;
a summed waveform generator for generating a summed waveform by summing a plurality of analog periodic waveforms obtained by said analog periodic waveform generator from digital periodic signals displaced along time axis; and
an analog/digital converter for converting said summed waveform to a digital waveform.
2. A phase interpolator as claimed in claim 1 , wherein said analog periodic waveform generator includes a sine wave generating circuit, and said weighting control circuit includes a plurality of transfer gates connected in parallel and controlled for connection.
3. A phase interpolator as claimed in claim 2 , wherein each transfer gate in said weighting control circuit has a transistor of the same size, and the weighting of said analog periodic waveform is controlled by controlling the number of transfer gates caused to conduct.
4. A phase interpolator as claimed in claim 2 , wherein each transfer gate in said weighting control circuit has a transistor of a different size, and the weighting of said analog periodic waveform is controlled by causing at least one transfer gate having a transistor of a prescribed size to conduct.
5. A phase interpolator as claimed in claim 1 , wherein said analog periodic waveform generator includes a plurality of CMOS inverters, and said weighting control circuit controls the number of CMOS inverters to be connected.
6. A phase interpolator as claimed in claim 1 , wherein said analog periodic waveform generator includes a plurality of CMOS inverter output stages, and said weighting control circuit controls the number of output transistors forming said plurality of CMOS inverter output stages.
7. A phase interpolator as claimed in claim 1 , wherein said analog periodic waveform generator is a high-frequency attenuation circuit for attenuating high-frequency components of said digital periodic signal, and said weighting control circuit converts an output of said high-frequency attenuation circuit into a current using a variable transconductor and applies said converted current to a common terminal.
8. A phase interpolator as claimed in claim 1 , wherein said analog periodic waveform generator is an integrator circuit.
9. A phase interpolator as claimed in claim 1 , wherein said analog periodic waveform generator and said summed waveform generating circuit comprise:
a current polarity switching circuit for switching the polarity of a current flowing from a constant current source to a common capacitive load by said digital periodic signal; and
a current value control circuit for controlling a current value of said current source.
10. A phase interpolator as claimed in claim 9 , wherein said current value control circuit controls the current value of said current source by an output of a D/A converter.
11. A phase interpolator as claimed in claim 1 , wherein said analog/digital converter is a comparator for comparing said summed waveform with a reference level for conversion into a digital waveform.
12. A phase interpolator as claimed in claim 1 , wherein said weighting control circuit includes a current output D/A converter, and an output of said D/A converter is controlled by being switched for connection to either a capacitive-coupled terminal or its complementary terminal.
13. A phase interpolator as claimed in claim 1 , wherein said weighting control circuit is configured to vary the number of current sources to be connected to a load capacitance terminal.
14. A phase interpolator as claimed in claim 1 , wherein said weighting control circuit includes a clamp circuit for holding a terminal voltage level within a fixed range.
15. A phase interpolator as claimed in claim 1 , wherein said phase interpolator is configured so that the size of transistors to be switched and the quantization step size of a D/A converter are made variable to provide a desired linearity characteristic to a timing output versus a control signal.