Temperature compensation circuit and method
View Patent ↗Disclosed are various embodiments of temperature-compensated relaxation oscillator circuits that may be fabricated using conventional CMOS manufacturing techniques. The relaxation oscillator circuits described herein exhibit superior low temperature coefficient performance characteristics, and do not require the use of expensive off-chip high precision resistors to effect temperature compensation. Positive and negative temperature coefficient resistors arranged in a resistor array offset one another to provide temperature compensation in the relaxation oscillator circuit.
1. A relaxation oscillator circuit, comprising:
a relaxation oscillator having an input, the relaxation oscillator being configured to provide an output signal having a frequency;
a field effect transistor (FET);
a current mirror circuit configured to provide a charging current to the input of the relaxation oscillator and a biasing current to a drain of the FET;
an operational amplifier having an output operably connected to a gate of the FET;
a band-gap circuit operably connected to a first input of the operational amplifier, and
a resistor array circuit having an output operably connected to a source of the FET and a second input of the operational amplifier;
wherein the resistor array circuit further comprises an array of positive temperature coefficient resistors arranged in parallel respecting one another and in parallel with respect to an array of negative temperature coefficient resistors arranged in parallel respecting one another, values of resistances provided by the positive temperature coefficient resistor array and the negative temperature coefficient resistor array being selectively controllable and selectable using switches operably connected to each of the resistors in the positive and negative arrays such that the frequency of the output signal remains substantially constant despite changes in the ambient temperature to which the relaxation oscillator circuit is subjected, the relaxation oscillator circuit having a temperature coefficient less than or equal to about 10 ppm/° C., the relaxation oscillator circuit further being one of a CMOS circuit and a BiCMOS circuit disposed on a single chip or integrated circuit.
2. The relaxation oscillator circuit of claim 1 , wherein the positive temperature coefficient resistor array comprises diffusion resistor, a high-poly resistor, or an nwell resistor.
3. The relaxation oscillator circuit of claim 1 , wherein the negative temperature coefficient resistor array comprises a high-poly resistor.
4. The relaxation oscillator circuit of claim 1 , wherein the frequency of the output signal remains substantially constant over temperatures ranging between about −40 degrees Celsius and about +125 degrees Celsius.
5. The relaxation oscillator circuit of claim 1 , wherein the output signal is a clock signal.
6. The relaxation oscillator circuit of claim 1 , wherein the frequency of the output signal is programmable.
7. The relaxation oscillator circuit of claim 1 , wherein the temperature coefficient of the relaxation oscillator circuit is less than or equal to about 5 ppm/° C.
8. A relaxation oscillator circuit, comprising:
a relaxation oscillator having an input, the relaxation oscillator being configured to provide an output signal having a frequency;
a field effect transistor (FET);
a current mirror circuit configured to provide a charging current to the input of the relaxation oscillator and a biasing current to a drain of the FET;
an operational amplifier having an output operably connected to a gate of the FET;
a band-gap circuit operably connected to a first input of the operational amplifier, and
a resistor array circuit having an output operably connected to a source of the FET and a second input of the operational amplifier;
wherein the resistor array circuit further comprises an array of positive temperature coefficient resistors arranged in parallel respecting one another and in series respecting an array of negative temperature coefficient resistors arranged in parallel respecting one another, values of resistances provided by the positive temperature coefficient resistor array and the negative temperature coefficient resistor array being selectively controllable and selectable using switches operably connected to each of the resistors in the positive and negative arrays such that the frequency of the output signal remains substantially constant despite changes in the ambient temperature to which the relaxation oscillator circuit is subjected, the relaxation oscillator circuit having a temperature coefficient less than or equal to about 10 ppm/° C., the relaxation oscillator circuit further being one of a CMOS circuit and a BiCMOS circuit disposed on a single chip or integrated circuit.
9. The relaxation oscillator circuit of claim 8 , wherein the positive temperature coefficient resistor array comprises a diffusion resistor, a high-poly resistor, or an nwell resistor.
10. The relaxation oscillator circuit of claim 8 , wherein the negative temperature coefficient resistor array comprises a high-poly resistor.
11. The relaxation oscillator circuit of claim 8 , wherein the frequency of the output signal remains substantially constant over temperatures ranging between about −40 degrees Celsius and about +125 degrees Celsius.
12. The relaxation oscillator circuit of claim 8 , wherein the output signal is a clock signal.
13. The relaxation oscillator circuit of claim 8 , wherein the frequency of the output signal is programmable.
14. The relaxation oscillator circuit of claim 8 , wherein the temperature coefficient of the relaxation oscillator circuit is less than or equal to about 5 ppm/° C.
15. A method of compensating for variations in a frequency of an output signal provided by a relaxation oscillator circuit, where the variations would otherwise be induced by changes in ambient temperature, comprising:
providing a relaxation oscillator having an input, the relaxation oscillator being configured to provide an output signal having a frequency;
providing a field effect transistor (FET);
providing a current mirror circuit configured to provide a charging current to the input of the relaxation oscillator and a biasing current to a drain of the FET;
providing an operational amplifier having an output operably connected to a gate of the FET;
providing a band-gap circuit operably connected to a first input of the operational amplifier, and
providing a resistor array circuit having an output operably connected to a source of the FET and a second input of the operational amplifier, wherein the resistor array circuit further comprises an array of positive temperature coefficient resistors arranged in parallel respecting one another and in parallel with respect to an array of negative temperature coefficient resistors arranged in parallel respecting one another, values of resistances provided by the positive temperature coefficient resistor array and the negative temperature coefficient resistor array being selectively controllable and selectable using switches operably connected to each of the resistors in the positive and negative arrays such that the frequency of the output signal remains substantially constant despite changes in the ambient temperature to which the relaxation oscillator circuit is subjected, the relaxation oscillator circuit having a temperature coefficient less than or equal to about 10 ppm/° C., the relaxation oscillator circuit further being one of a CMOS circuit and a BiCMOS circuit disposed on a single chip or integrated circuit.
16. A method of compensating for variations in a frequency of an output signal provided by a relaxation oscillator circuit, where the variations would otherwise be induced by changes in ambient temperature, comprising:
providing a relaxation oscillator having an input, the relaxation oscillator circuit being configured to provide an output signal having a frequency;
providing a field effect transistor (FET);
providing a current mirror circuit configured to provide a charging current to the input of the relaxation oscillator and a biasing current to a drain of the FET;
providing an operational amplifier having an output operably connected to a gate of the FET;
providing a band-gap circuit operably connected to a first input of the operational amplifier, and
providing a resistor array circuit having an output operably connected to a source of the FET and a second input of the operational amplifier, wherein the resistor array circuit further comprises an array of positive temperature coefficient resistors arranged in parallel respecting one another and in series respecting an array of negative temperature coefficient resistors arranged in parallel respecting one another, values of resistances provided by the positive temperature coefficient resistor array and the negative temperature coefficient resistor array being selectively controllable and selectable using switches operably connected to each of the resistors in the positive and negative arrays such that the frequency of the output signal remains substantially constant despite changes in the ambient temperature to which the relaxation oscillator circuit is subjected, the relaxation oscillator circuit having a temperature coefficient less than or equal to about 10 ppm/° C., the relaxation oscillator circuit further being one of a CMOS circuit and a BiCMOS circuit disposed on a single chip or integrated circuit.