System and method for analyzing CPU performance from a serial link front side bus
Monitoring of boot progress for a multiprocessor information handling system is performed with a test module running on a CPLD. RAM integrated in the CPLD stores boot progress information passed through an I/O buffer located between the processors and the firmware that boots the processors. Downloading of the boot progress from the RAM to an external device, such as through a serial port, provides a processor trace that is analysis and debugging of the firmware by recording processor operations through the boot progress.
1. An information handling system comprising:
plural processors operable to process information;
a front side bus interfacing the processors with a serial link;
firmware operable to boot the processors from an off state to an operational state with boot instructions executed on the processors;
an I/O buffer interfacing the firmware with the processors;
a Complex Programmable Logic Device (CPLD) interfaced with the I/O buffer and having integrated memory, the CPLD operable to monitor the boot instructions and store boot progress based upon boot instructions executed for each processor as indicated by communications through the I/O buffer, the CPLD storing the boot progress in the integrated memory; and
a switch interfaced with the CPLD and operable to command download of the stored boot progress from the integrated memory.
2. The information handling system of claim 1 wherein the boot progress comprises launching of each processor by the firmware.
3. The information handling system of claim 1 wherein the boot progress comprises execution by each processor of boot instructions.
4. The information handling system of claim 1 wherein the boot progress comprises initialization of the front side bus by the firmware.
5. The information handling system of claim 1 further comprising DRAM wherein the boot progress comprises DRAM initialization and timing.
6. The information handling system of claim 1 further comprising a northbridge wherein the boot progress comprises northbridge initialization.
7. The information handling system of claim 1 wherein the CPLD retrieves information communicated across the I/O buffer by the firmware and processors.
8. The information handling system of claim 1 wherein the switch commands download of the stored boot progress to a serial port.
9. A method for monitoring boot progress of a multiprocessor information handling system having plural processors, the method comprising:
generating boot instructions with firmware;
communicating the boot instructions to the processors through an I/O buffer;
communicating boot progress from the processors through the I/O buffer;
monitoring execution of the boot instructions by the plural processors with a CPLD by retrieving boot progress from the I/O buffer to the CPLD; and
storing boot progress in memory associated with the CPLD.
10. The method of claim 9 further comprising downloading the stored boot progress from the memory through a serial bus.
11. The method of claim 9 wherein the boot progress comprises launching of each processor by the firmware.
12. The method of claim 9 wherein the boot progress comprises execution by each processor of boot instructions.
13. The method of claim 9 wherein the boot progress comprises initialization of the front side bus by the firmware.
14. The method of claim 9 wherein the boot progress comprises DRAM initialization and timing.
15. The method of claim 9 wherein the boot progress comprises northbridge initialization.
16. The method of claim 9 wherein monitoring execution of the boot instructions with a CPLD further comprises copying boot instructions to the CPLD from the I/O buffer.
17. The method of claim 9 further comprising:
halting the boot progress;
maintaining power to the CPLD;
retrieving the boot progress from the memory; and
powering down the CPLD.
18. A system for tracing boot progress of plural processor in a multiprocessor information handling system, the system comprising:
firmware operable to generate boot instructions for the plural processors to execute;
an I/O buffer interfaced with the firmware and the plural processors, the I/O buffer operable store the boot instructions from the firmware for use by the plural processors and to receive boot progress information from the plural processors;
a CPLD interfaced with the I/O buffer, the CPLD having integrated memory; and
a test module running on the CPLD and operable to retrieve the boot instructions and boot progress information from the I/O buffer and store the boot instructions and boot progress information in the integrated memory.
19. The system of claim 18 wherein the I/O buffer is further operable to receive boot information from the processors for use by the firmware, and wherein the test module is further operable to store the boot information in the integrated memory.
20. The system of claim 18 further comprising a test switch interfaced with the test module and operable to initiate transfer of the boot instructions from the integrated memory to a port for communication to an external device.