IP Library › Granted Patent US 8,071,423
Granted Patent B2
US 8,071,423 · App. 12/652,451 · Granted Dec 6, 2011

Variable resistance memory devices and methods of forming variable resistance memory devices

Assignee: Samsung Electronics Co. Ltd.
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Quick Facts
Patent No.
US 8,071,423
App. No.
12/652,451
Granted
Dec 6, 2011
Kind
B2
Abstract

Provided are variable resistance memory devices and methods of forming the variable resistance memory devices. The methods can include forming an etch stop layer on an electrode, forming a molding layer on the etch stop layer, forming a recess region including a lower part having a first width and an upper part having a second width by recessing the etch stop layer and the molding layer, and forming a layer of variable resistance material in the recess region.

Claims (24)

1. A method of forming a variable resistance memory device, the method comprising:

forming an etch stop layer on an electrode;

forming a molding layer on the etch stop layer;

forming a recess region including a first part through the etch stop layer having a first width and a second part through the molding layer having a second width by recessing the etch stop layer and the molding layer wherein the first and second widths are different; and

forming a layer of variable resistance material in the recess region,

wherein the forming of the recess region includes:

forming a first recess region having the first width by recessing the molding layer and the etch stop layer; and

forming a second recess region having the second width by recessing the molding layer.

2. The method of claim 1 , wherein the first width is narrower than the second width.

3. The method of claim 1 , wherein the layer of variable resistance material is a layer of phase change material.

4. The method of claim 1 , wherein the forming of the recess region includes recessing a portion of the electrode.

5. The method of claim 1 , wherein the forming of the second recess region selectively etches the molding layer while maintaining the etch stop layer.

6. The method of claim 5 , wherein the etch stop layer is a silicon nitride layer, and the molding layer is a silicon oxide layer.

7. A method of forming a variable resistance memory device, the method comprising:

forming an etch stop layer on an electrode;

forming a molding layer on the etch stop laver;

forming a recess region including a first part through the etch stop layer having a first width and a second part through the molding layer having a second width by recessing the etch stop layer and the molding layer wherein the first and second widths are different; and

forming a layer of variable resistance material in the recess region, wherein the forming of the recess region includes:

forming a first recess region having the first width by recessing the molding layer;

masking portions of the etch stop layer by forming spacers on sidewalls of the first recess region;

forming a second recess region having the second width by recessing portions of the etch stop layer exposed between the spacers; and

removing the spacers.

8. The method of claim 7 , wherein removing the spacers includes forming a third recess region having a third width by recessing the molding layer, the third width being wider than the first width.

9. The method of claim 7 , wherein the spacers are silicon oxide spacers or silicon oxynitride spacers.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2023
From: SAMSUNG ELECTRONICS CO., LTD.
To: IMBERATEK, LLC.
Reel/Frame 062819/0268 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2010
From: JOO, HEUNG JIN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 023811/0560 →
Priority Claims (1)
KR 10-2009-0000854 · Jan 6, 2009 · national
Continuity (1)
Related Publication 20100173479A1 · Jul 8, 2010