Transistor with embedded Si/Ge material having reduced offset to the channel region
A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.
1. A method, comprising:
forming cavities in a silicon-containing crystalline semiconductor region adjacent to a gate electrode structure of a transistor of a semiconductor device, wherein said gate electrode structure comprises an offset sidewall spacer, and said cavities comprise an under-etched region extending under at least said offset sidewall spacer;
after forming said cavities comprising said under-etched region, forming a protection layer on all exposed surfaces of said cavities;
introducing said semiconductor device into a process ambient at an elevated first temperature after forming said protection layer;
adjusting said process ambient so as to have a second lower temperature;
removing said protection layer in said process ambient; and
forming a semiconductor alloy in said cavities in said process ambient at said second temperature.
2. The method of claim 1 , wherein forming said cavities comprises performing a first etch process comprising a plasma ambient and performing a second etch process comprising a wet etch chemistry.
3. The method of claim 2 , wherein said wet etch chemistry has a crystallographically anisotropic removal rate.
4. The method of claim 3 , wherein said wet etch chemistry comprises tetra methyl ammonium hydroxide (TMAH).
5. The method of claim 1 , wherein forming said protection layer comprises forming an oxide layer on said exposed surfaces of said cavities.
6. The method of claim 5 , wherein said oxide layer is formed in an oxidizing gas atmosphere at a temperature of approximately less than 750° C.
7. The method of claim 5 , wherein said oxide layer is formed by performing a wet chemical oxidation process.
8. The method of claim 1 , further comprising forming drain and source regions at least partially in said semiconductor alloy.
9. The method of claim 1 , wherein said semiconductor alloy is formed so as to induce a compressive strain in a channel region of said transistor.
10. The method of claim 9 , wherein said semiconductor alloy is comprised of silicon and germanium.
11. The method of claim 1 , wherein said first elevated temperature is approximately 800° C. or higher.
12. A method comprising:
forming cavities in a crystalline semiconductor region laterally offset to a gate electrode structure of a transistor by performing a first etch process comprising a plasma ambient and a second etch process comprising a wet etch chemistry, wherein said cavities comprise an under-etched region extending under at least a sidewall spacer structure of said gate electrode structure;
forming a protection layer on all exposed surfaces of said cavities;
introducing said transistor into a process ambient at an elevated temperature after forming said protection layer;
removing said protection layer in said process ambient;
forming a strain-inducing semiconductor alloy in said cavities; and
forming drain and source regions in said semiconductor region.
13. The method of claim 12 , further comprising establishing a deposition temperature in said process ambient prior to removing said protection layer.
14. The method of claim 13 , wherein said deposition temperature is approximately 750° C. or less.
15. The method of claim 12 , wherein said protection layer is formed as a silicon dioxide material.
16. The method of claim 12 , wherein said wet etch chemistry of said second etch process has a crystallographically anisotropic etch behavior.
17. The method of claim 12 , wherein said semiconductor alloy comprises at least one of germanium and tin.