Power and ground routing of integrated circuit devices with improved IR drop and chip performance
An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective the plurality of IMD layers, wherein the first conductive layers comprise copper; a first passivation layer overlying the plurality of IMD layers and the plurality of first conductive layers; a plurality of first power/ground mesh wiring lines, formed in a second conductive layer overlying the first passivation layer, for distributing power signal or ground signal, wherein the second conductive layer comprise aluminum; and a second passivation layer covering the second conductive layer and the first passivation layer.
1. An integrated circuit chip comprising:
a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper;
a first passivation layer overlying said plurality of IMD layers and said plurality of first conductive layers;
a plurality of first power/ground mesh wiring lines, formed in a second conductive layer overlying said first passivation layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and
a second passivation layer covering said second conductive layer and said first passivation layer.
2. The integrated circuit chip of claim 1 , wherein said integrated circuit chip further comprises:
a plurality of second power/ground mesh wiring lines, formed in a topmost layer of said plurality of first conductive layers, for distributing power signal or ground signal; wherein said second power/ground mesh wiring lines comprise a plurality of horizontal trace lines or longitudinal trace lines.
3. The integrated circuit chip of claim 2 wherein said plurality of first power/ground mesh wring line has a thickness that is greater than that of said second power/ground mesh wiring line.
4. The integrated circuit chip of claim 1 wherein said first power/ground mesh wiring lines comprise a plurality of horizontal trace lines or longitudinal trace lines.
5. The integrated circuit chip of claim 1 , wherein said integrated circuit chip further comprises:
a first power/ground ring formed in said second conductive layer.
6. The integrated circuit chip of claim 1 , wherein said integrated circuit chip further comprises:
a second power/ground ring formed in a topmost layer of said plurality of first conductive layers.
7. An integrated circuit chip comprising:
a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper;
a first passivation layer overlying said plurality of IMD layers and said plurality of first conductive layers;
a first power/ground ring, formed in a second conductive layer overlying said first passivation layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and
a second passivation layer covering said second conductive layer and said first passivation layer.
8. The integrated circuit chip of claim 7 , wherein said integrated circuit chip further comprises:
a second power/ground ring, formed in a topmost layer of said plurality of first conductive layers, for distributing power signal or ground signal.
9. The integrated circuit chip of claim 8 wherein said first power/ground ring has a thickness that is greater than that of said second power/ground ring.
10. The integrated circuit chip of claim 7 , wherein said integrated circuit chip further comprises:
a plurality of first power/ground mesh wiring lines, formed in said second conductive layer, for distributing power signal or ground signal; wherein said plurality of first power/ground mesh wiring lines comprise a plurality of horizontal trace lines or longitudinal trace lines.
11. The integrated circuit chip of claim 7 , wherein said integrated circuit chip further comprises:
a plurality of second power/ground mesh wiring lines, formed in a topmost layer of said plurality of first conductive layers, for distributing power signal or ground signal; wherein said plurality of second power/ground mesh wiring lines comprise a plurality of horizontal trace lines or longitudinal trace lines.