Polarity dependent switch for resistive sense memory
View Patent ↗A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.
1. A memory unit, comprising:
a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell;
a semiconductor transistor in electrical connection with the resistive sense memory cell, the semiconductor transistor comprising a gate element formed on a substrate, the semiconductor transistor comprises a source contact and a bit contact, the gate element electrically connecting the source contact and the bit contact, the resistive sense memory cell electrically connected to the bit contact, the source contact being more heavily implanted with dopant material than the bit contact.
2. A memory unit according to claim 1 , wherein the source contact includes a lightly doped drain region.
3. A memory unit according to claim 1 , wherein the source contact is halo implanted with a dopant material.
4. A memory unit according to claim 3 , wherein the dopant material is boron.
5. A memory unit according to claim 3 , wherein the bit contact includes a lightly doped drain region.
6. A memory unit according to claim 3 , wherein the bit contact is not halo implanted with a dopant material.
7. A memory unit according to claim 1 , wherein the resistive sense memory cell comprises a spin-torque transfer memory cell.
8. A memory unit according to claim 1 , wherein a write current in an easy direction passes through the source contact before the bit contact, and a write current in a hard direction passes through the bit contact before the source contact.
9. A memory unit according to claim 1 , wherein the memory unit includes only a single semiconductor transistor in electrical connection with a single resistive sense memory cell.
10. A memory unit according to claim 1 , wherein the memory unit further includes a second semiconductor transistor in electrical connection with the resistive sense memory cell.
11. A memory unit, comprising:
a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell;
a first switching device in electrical connection with the resistive sense memory cell, the first switching device comprising a first gate element formed on a substrate, the first switching device comprises a first source contact and a common bit contact, the first gate element electrically connecting the first source contact and the common bit contact, the resistive sense memory cell electrically connected to the common bit contact, the first source contact being more heavily implanted with dopant material than the common bit contact; and a second switching device in electrical connection with the resistive sense memory cell, the second switching device comprising a second gate element formed on the substrate, the second switching device comprises a second source contact and the common bit contact, the second gate element electrically connecting the second source contact and the common bit contact, the resistive sense memory cell electrically connected to the common bit contact, the second source contact being more heavily implanted with dopant material than the common bit contact.
12. A memory unit according to claim 11 , wherein the first source contact and the second source contact are implanted with more dopant material than the common bit contact.
13. A memory unit according to claim 10 , wherein the first source contact and second source contact is halo implanted with a dopant material.
14. A memory unit according to claim 13 , wherein the common bit contact includes a lightly doped drain region.
15. A memory unit according to claim 14 , wherein the common bit contact is not halo implanted with a dopant material.
16. A memory unit according to claim 11 , wherein the resistive sense memory cell comprises a spin-torque transfer memory cell.
17. A memory unit according to claim 11 , wherein the first source contact and the second source contact are electrically connected to a common source line.
18. A memory unit according to claim 11 , wherein the first gate contact and second gate contact are electrically connected to a common word line.
19. A select device comprising;
a semiconductor transistor comprising a gate element formed on a substrate, the semiconductor transistor comprises a source contact and a bit contact, the gate element electrically connecting the source contact and the bit contact, the source contact being more heavily implanted with dopant material than the bit contact.
20. A select device according to claim 19 , wherein the source contact is halo implanted with a dopant material and the bit contact is not halo implanted with a dopant material.