IP Library › Granted Patent US 8,077,440
Granted Patent B2
US 8,077,440 · App. 12/663,287 · Granted Dec 13, 2011

ESD protection circuit

Assignee: NXP B.V.
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Quick Facts
Patent No.
US 8,077,440
App. No.
12/663,287
Granted
Dec 13, 2011
Kind
B2
Abstract

An ESD protection circuit comprises a first supply line (V DD ), a second supply line (V ss ), an ESD protection device, preferably being configured as a transistor (M P ), which is connected between the first and second supply line (V DD , V SS ) and at least one pin (V A ) connected to the first and second supply lines (V DD , V SS ) via diodes D1, D2. The ESD protection device is controllable by a trigger voltage that is set by a trigger voltage setting circuit (R P , R D , Z1, Z2, Z3). The ESD protection circuit comprises a trigger circuit ( 1 ) being connected to the at least one pin (V A ) and providing pin specific trigger voltages, wherein the trigger circuit ( 1 ) is further connected to the trigger voltage setting circuit.

Claims (14)

1. A circuit comprising:

a first supply line, a second supply line, and an electro static discharge (ESD) protection device connected between the first and second supply lines; and

at least one pin connected to the first and second supply lines via diodes;

wherein the ESD protection device comprises a trigger circuit connected to the at least one pin, wherein the trigger circuit provides a first pin specific trigger voltage and a second pin specific trigger voltage;

wherein the first pin specific trigger voltage occurs between the at least one pin and the first supply line, and the second pin specific trigger voltage occurs between the at least one pin and the second supply line;

wherein the first pin specific trigger voltage and the second pin specific trigger voltage are set by a trigger-voltage setting-circuit, wherein the trigger circuit is further connected to the trigger-voltage setting-circuit.

2. The circuit as claimed in claim 1 , wherein the trigger circuit comprises a plurality of electronic switching devices controllable by a voltage applied to the at least one pin, wherein the electronic switching devices are connected in parallel to portions of the trigger-voltage setting-circuit.

3. The circuit as claimed in claim 2 , wherein the portions of the trigger-voltage setting-circuit to which the electronic switching devices are connected in parallel comprise at least one zener diode.

4. The circuit as claimed in claim 2 , wherein the trigger circuit further comprises at least one zener diode, wherein the zener diode is serially connected to at least one of the plurality of electronic switching devices and to the trigger-voltage setting-circuit.

5. The circuit as claimed in claim 2 , wherein the plurality of electronic switching devices comprise a first transistor and a second transistor.

6. The circuit as claimed in claim 5 , wherein a drain of the first transistor is connected to the first supply line, a gate of the first transistor is connected to the at least one pin, and a source of the first transistor is connected to a cathode terminal of a zener diode, wherein an anode terminal of the zener diode is connected to the trigger-voltage setting-circuit.

7. The circuit as claimed in claim 5 , wherein a drain of the second transistor is connected to a resistor, a gate of the second transistor is connected to the at least one pin, and a source of the second transistor is connected to an anode of a zener diode, wherein a cathode of the zener diode is connected to the trigger-voltage setting-circuit.

8. The circuit as claimed in claim 1 , wherein the first pin specific trigger voltage is different from the second pin specific trigger voltage.

9. The circuit as claimed in claim 1 , wherein the trigger-voltage setting-circuit sets a supply trigger voltage, wherein the supply trigger voltage occurs between the first supply line and the second supply line.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2009
From: KRABBENBORG, BERNARDUS HENRICUS (BENNO); BERKHOUT, MARCO; VAN ZWOL, JOHANNES
To: NXP, B.V.
Reel/Frame 023618/0813 →
Priority Claims (1)
EP 07110776 · Jun 21, 2007 · regional
Continuity (1)
Related Publication 20100220419A1 · Sep 2, 2010