Memory and method for sensing data in a memory using complementary sensing scheme
View Patent ↗In a memory ( 100 ), a local data line pair ( 116, 118 ) is precharged to a first logic state and a global data line pair ( 101, 104 ) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair ( 116, 118 ) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair ( 101, 104 ) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.
1. A method for sensing data in a memory comprising:
precharging a local data line pair to a first logic state and a global data line pair to a second logic state;
coupling a selected memory cell to said local data line pair to develop a differential local data line voltage;
subsequently amplifying said differential local data line voltage to form an amplified differential local data line voltage; and
driving a selected one of said global data line pair to said first logic state in response to said amplified differential local data line voltage to form a differential global data line voltage.
2. The method of claim 1 further comprising:
subsequently amplifying said differential global data line voltage to form an amplified differential global data line voltage.
3. The method of claim 2 further comprising:
outputting a data output signal in response to said amplified differential global data line voltage.
4. The method of claim 2 wherein said subsequently amplifying said differential global data line voltage comprises:
starting to amplify said differential global data line voltage after starting to amplify said differential local data line voltage.
5. The method of claim 2 wherein said subsequently amplifying said differential global data line voltage comprises:
subsequently amplifying said differential global data line voltage while continuing to amplify said differential local data line voltage, and continuing to amplify said global data line voltage while ceasing to amplify said differential local data line voltage.
6. The method of claim 2 wherein said subsequently amplifying said differential global data line voltage further comprises:
subsequently activating a global sense amplifier after a programmable delay determined in response to a state of at least one fuse.
7. The method of claim 1 wherein said precharging comprises:
precharging said local data line pair to a logic high state and said global data line pair to a logic low state.
8. The method of claim 1 wherein said subsequently amplifying said differential local data line voltage comprises:
subsequently activating a local sense amplifier after a first programmable delay determined in response to a state of at least one fuse.
9. The method of claim 8 further comprising:
subsequently activating a global sense amplifier after a second programmable delay determined in response to a state of at least one other fuse.
10. The method of claim 1 wherein said subsequently amplifying said differential local data line voltage comprises:
subsequently activating a selected local sense amplifier of a plurality of local sense amplifiers.
11. A method for accessing data in a memory comprising:
precharging a local data line pair to a first logic state;
during a first time period, coupling a memory cell to said local data line pair, and precharging a global data line pair to a second logic state;
during a subsequent second time period, amplifying a difference in voltage between first and second local data lines of said local data line pair, driving a selected global data line of said global data line pair to said first logic state in response to a sensed voltage on said local data line pair, and amplifying a difference in voltage between first and second global data lines of said global data line pair; and
during a subsequent third time period, latching said difference in voltage between said first and second global data lines of said global data line pair, and precharging said local data line pair to said first logic state in preparation for a subsequent access.
12. The method of claim 11 , further comprising the step of:
starting to amplify said difference in voltage between said first and second global data lines of said global data line pair a first programmable delay time after starting to amplify said difference in voltage between said first and second local data lines of said local data line pair.
13. The method of claim 11 wherein said latching comprises:
keeping a global sense amplifier active, thereby holding said difference in voltage between said first and second global data lines of said global data line pair.
14. The method of claim 11 wherein coupling said memory cell to said local data line pair comprises:
coupling a bit line pair to which said memory cell is coupled to said local data line pair.
15. A method for sensing data in a memory comprising:
precharging a local data line pair to a first logic state;
precharging a global data line pair to a second logic state;
coupling a selected memory cell to said local data line pair to develop a differential voltage on said local data line pair;
amplifying said differential voltage on said local data line pair;
driving a differential voltage on said global data line pair in response to said differential voltage on said local data line pair; and
amplifying said differential voltage on said global data line pair while amplifying said differential voltage on said local data line pair.
16. The method of claim 15 wherein said amplifying said differential voltage on said global data line pair comprises:
beginning to amplify said differential voltage on said global data line pair after beginning to amplify said differential voltage on said local data line pair, and continuing to amplify said differential voltage on said global data line pair while ceasing to amplify said differential voltage on said local data line pair.
17. The method of claim 15 wherein said precharging said local data line pair to said first logic state comprises precharging said local data line pair to a logic high state, and said precharging said global data line pair to said second logic state comprises precharging said global data line pair to a logic low state.
18. The method of claim 15 wherein said amplifying said differential voltage on said local data line pair comprises:
activating a local sense amplifier after a first programmable delay determined in response to a state of at least one fuse.
19. The method of claim 18 wherein said activating said differential voltage on said global data line pair comprises:
activating a global sense amplifier after a second programmable delay determined in response to a state of at least one other fuse.
20. The method of claim 15 wherein said driving said differential voltage on said global data line pair comprises:
driving a selected one of said global data line pair to said first logic state in response to said differential voltage on said local data line pair to form said differential voltage on said global data line pair.