Image sensor with a gated storage node linked to transfer gate
A CMOS imaging system with increased charge storage of pixels yet decreased physical size, kTC noise and active area. A storage node is connected to the transfer gate and provides a storage node for a pixel, allowing for kTC noise reduction prior to readout. The pixel may be operated with the shutter gate on during the integration period to increase the amount of time for charge storage by a pixel.
1. A pixel circuit formed on a substrate for use in an imaging device, said pixel circuit comprising:
a photosensor for generating charge during an integration period;
a shutter transistor connected to said photosensor to transfer charge from said photosensor;
a storage node formed by a depletion region that is at least partially within the substrate, the storage node being connected to said shutter transistor to receive said charge transferred by said shutter transistor;
a barrier region located within the substrate between the photosensor and the storage node, the barrier region being opposingly doped than the storage node and being coupled to and controlled by the shutter transistor;
a transfer gate connected to said storage node to transfer charge from said storage node;
a floating diffusion node connected to said transfer gate to receive said charge from said transfer gate; and
a readout circuit connected to said floating diffusion node to output a signal based on the charge accumulated at the floating diffusion node.
2. A pixel circuit formed on a substrate comprising:
a photosensor for accumulating charge;
a first transistor for transferring charge from said photosensor to a first storage node, wherein said first storage node is formed by a depletion region that is at least partially within the substrate;
a barrier region located within the substrate between the photosensor and the first storage node, the barrier region being opposingly doped than the first storage node and being coupled to and controlled by the first transistor;
a second transistor for transferring charge from said first storage node to a second storage node; and
a readout circuit for providing a pixel output signal based on charges transferred to said second storage node.
3. The circuit of claim 2 , wherein said readout circuit further comprises:
a reset transistor connected to said second storage node for resetting the voltage on the second storage node;
a source-follower transistor connected to said reset transistor for receiving charge from the second storage node; and
a row select transistor connected to said source-follower transistor for outputting a signal produced by said source follower transistor.
4. The circuit of claim 2 , wherein said first storage node is formed within said pixel.
5. The circuit of claim 2 , wherein said barrier region is comprised of boron.
6. The circuit of claim 2 , wherein said first transistor is an electronic shutter for said pixel circuit.
7. The circuit of claim 2 , wherein said first transistor remains on during the integration period.
8. The circuit of claim 2 , wherein said pixel circuit is a CMOS pixel.
9. The circuit of claim 2 , wherein said pixel circuit comprises five transistors.
10. A pixel sensor array formed on a substrate comprising:
a plurality of pixels, each pixel comprising:
a photosensor for generating charge during an integration period;
a shutter transistor connected to said photosensor to transfer charge from said photosensor;
a storage node formed by a depletion region that is at least partially within the substrate, the storage node being connected to said shutter transistor to receive said charge transferred by said shutter transistor;
a barrier region located within the substrate between said photosensor and said storage node, the barrier region being opposingly doped than the storage node and being coupled to and controlled by the shutter transistor;
a transfer gate connected to said storage node to transfer charge from said storage node;
a floating diffusion node connected to said transfer gate to receive said charge from said storage node; and
a readout circuit connected to said floating diffusion node to output the charge accumulated at the floating diffusion node.
11. A pixel sensor array formed on a substrate comprising:
a plurality of pixels, each pixel comprising:
a photosensor for accumulating charge;
a first transistor for transferring charge from said photosensor to a first storage node, wherein said first storage node is formed by a depletion region that is at least partially within the substrate;
a barrier region located within the substrate between the photosensor and the first storage node, the barrier region being opposingly doped than the first storage node and being coupled to and controlled by the first transistor;
a second transistor for transferring charge from said first storage node to a second storage node; and
a readout circuit for providing a pixel output signal based on charges transferred to said second storage node.
12. The array of claim 11 wherein said readout circuit further comprises a reset transistor connected to said second storage node for resetting the voltage on the second storage node.
13. The array of claim 11 , wherein said first storage node is formed within said pixel.
14. The array of claim 11 , wherein said first transistor is an electronic shutter.
15. The array of claim 11 , wherein the first transistor remains on during the integration period.
16. The array of claim 11 , wherein said barrier region is comprised of boron.
17. The array of claim 11 , wherein each pixel is a CMOS pixel.
18. An imaging system comprising:
a processor; and
an imaging device comprising an array of pixels formed on a substrate, coupled to said imaging system each pixel comprising:
a photosensor for generating charge during an integration period;
a shutter transistor connected to said photosensor to transfer charge from said photosensor;
a storage node formed by a depletion region that is at least partially within the substrate, the storage node being connected to said shutter transistor to receive said charge transferred by said shutter transistor;
a barrier region located within the substrate between said photosensor and said storage node, the barrier region being opposingly doped than the storage node and being coupled to and controlled by the shutter transistor;
a transfer gate connected to said storage node to transfer charge from said storage node;
a floating diffusion node connected to said transfer gate to receive said charge from said storage node when said transfer gate is activated; and
a readout circuit connected to said floating diffusion node to output the charge accumulated at the floating diffusion node.
19. An imaging system comprising:
a processor; and
an imaging device comprising an array of pixels formed on a substrate, coupled to said imaging system each pixel comprising:
a photosensor for accumulating charge;
a first transistor for transferring charge from said photosensor to a first storage node, wherein said first storage node is formed by a depletion region that is at least partially within the substrate;
a barrier region located within the substrate between the photosensor and the first storage node, the barrier region being opposingly doped than the first storage node and being coupled to and controlled by the first transistor;
a second transistor for transferring charge from said first storage node to a second storage node; and
a readout circuit for providing a pixel output signal based on charges transferred to said second storage node.