Integrating a first contact structure in a gate last process

1. A method for fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate;

forming a transistor having a dummy gate structure on the semiconductor substrate;

forming a first dielectric layer over the substrate including the transistor;

forming a first contact feature in the first dielectric layer;

forming a dummy contact feature in the first dielectric layer;

removing a portion of the first dielectric layer to expose a portion of the dummy gate structure;

removing the dummy gate structure and replacing it with a metal gate;

forming a second dielectric layer over the first dielectric layer; and

forming a second contact feature and a metal barrier in the second dielectric layer, the second contact feature being coupled to the first contact feature via the metal barrier.

2. The method of claim 1 wherein the forming the dummy contact feature includes forming the dummy contact feature adjacent the transistor and substantially coplanar with the first contact feature.

3. The method of claim 1 wherein the removing the dummy gate structure and replacing it with a metal gate includes:

performing an etch back process to remove the dummy gate structure thereby forming a trench;

filling a portion of the trench with a work function metal layer;

filling the remaining portion of the trench with a filler metal layer; and

performing a CMP process on the filler metal layer and work function metal layer to form the metal gate.

4. The method of claim 1 further comprising forming a metal layer over the second dielectric layer, the metal layer being electrically coupled to the second contact feature.

5. The method of claim 1 wherein the forming the first contact feature and the second contact feature comprises forming the first contact feature to have a substantially same width as the second contact feature.

6. The method of claim 1 wherein the forming the first contact feature and the second contact feature comprises forming the first contact feature to have a substantially different width as the second contact feature.

7. A method comprising:

providing a substrate;

forming a transistor in the substrate, the transistor having a dummy gate;

forming an inter-level dielectric (ILD) layer over the substrate and transistor;

forming a contact feature in the ILD layer;

forming a dummy contact feature in the ILD layer, the dummy contact feature being substantially coplanar with the contact feature; and

after forming the contact feature, replacing the dummy gate of the transistor with a metal gate.

8. The method of claim 7 wherein the forming the contact feature in the ILD layer comprises forming a dual contact, the dual contact including a first contact feature and a second contact feature overlying the first contact feature, the second contact feature being coupled to the first contact feature.

9. The method of claim 8 wherein the forming the dual contact comprises forming a metal barrier layer on the sidewalls and bottom of the second contact feature, such that the metal barrier layer effects the coupling between the first and second contact features.

10. The method of claim 8 wherein the forming the dual contact including the first and second contact features comprises forming the first contact feature in a first ILD layer and forming the second contact feature in a second ILD layer.

11. The method of claim 7 wherein the replacing the dummy gate of the transistor with a metal gate comprises:

performing a chemical mechanical polishing (CMP) process on the ILD layer until the dummy gate is exposed;

performing an etch back process to remove the dummy gate, thereby forming a trench;

filling a portion of the trench with a work function metal layer;

filling the remaining portion of the trench with a filler metal layer; and

performing another CMP process on the filler metal layer and work function metal layer to form the metal gate.

12. The method of claim 11 wherein the forming the transistor comprises including a high-k dielectric layer in a gate stack of the transistor, the gate stack including the filler metal layer and work function metal layer.

13. A method comprising:

providing a semiconductor substrate having a first region and a second region;

forming a transistor having a dummy gate in the first region of the semiconductor;

forming an inter-level dielectric (ILD) layer over the semiconductor substrate and transistor;

forming a contact feature in the ILD layer in the first region and a dummy contact feature in the ILD layer in the second region; and

after forming the contact and dummy contact features, replacing the dummy gate of the transistor with a metal gate.

14. The method of claim 13 wherein the forming the contact feature and the dummy contact feature comprises forming a contact plug having a metal barrier layer surrounding the contact plug.

15. The method of claim 14 wherein the forming the contact plug having the metal barrier layer surrounding the contact plug comprises:

selecting a material for the contact plug from one of copper (Cu) and tungsten (W); and

selecting a material for the metal barrier layer from Ti, TiN, Ta, TaN, or combination thereof.

16. The method of claim 13 further comprising:

after replacing the dummy gate of the transistor with the metal gate, forming another ILD layer over the ILD layer having the contact and dummy contact features formed therein; and

forming another contact feature in the another ILD layer, the another contact feature being coupled to the contact feature in the ILD layer.

17. The method of claim 16 wherein the forming the another contact feature in the another ILD layer comprises forming a metal barrier layer on the sidewalls and bottom of the another contact feature, such that the metal barrier layer effects the coupling between the contact features of the ILD layers.

18. The method of claim 13 wherein the forming the contact feature in the ILD layer comprises coupling the contact feature to a doped region of the transistor.

19. The method of claim 13 wherein the replacing the dummy gate of the transistor with a metal gate comprises:

performing a chemical mechanical polishing (CMP) process on the ILD layer until the dummy gate is exposed;

performing an etch back process to remove the dummy gate, thereby forming a trench;

filling a portion of the trench with a work function metal layer;

filling the remaining portion of the trench with a filler metal layer; and

performing another CMP process on the filler metal layer and work function metal layer to form the metal gate.

20. The method of claim 13 wherein the forming the transistor comprises forming a high-k dielectric layer.