Integration of non-volatile charge trap memory devices and logic CMOS devices
A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.
1. A method of fabricating a semiconductor structure, the method comprising:
implanting a first dopant species into a first region of a semiconductor substrate to form an n-well for a PMOS transistor;
forming a non-volatile charge trapping dielectric stack over a second region of the semiconductor substrate after forming the PMOS transistor n-well, the non-volatile charge trapping dielectric stack including a blocking layer on a charge trapping layer over a tunneling layer formed on the semiconductor substrate;
forming a gate oxide of the PMOS transistor over the first region of the semiconductor substrate after forming the non-volatile charge trapping dielectric stack;
forming a PMOS gate stack and another MOS gate stack over the first region of the semiconductor substrate;
forming a first sidewall spacer adjacent to the PMOS gate stack and a second sidewall spacer adjacent to the another MOS gate stack;
implanting a source and drain into the first region adjacent to the first sidewall spacer prior to depositing a multi-layer liner;
depositing the multi-layer liner over the second sidewall spacer, the multi-layer liner including a top layer and a bottom layer;
etching the top layer selective to the bottom layer to form a disposable sidewall spacer separated from the second sidewall spacer by at least the bottom layer;
implanting a source and a drain offset from the second sidewall spacer by the disposable sidewall spacer to increase a breakdown voltage;
removing the disposable sidewall spacer selectively to the bottom layer; and
forming silicide over the first region of the semiconductor substrate while blocking formation of silicide over the non-volatile charge trapping dielectric stack.
2. The method of claim 1 , further comprising:
performing an implant photomask strip after implanting the first dopant species and prior to forming the non-volatile charge trapping dielectric stack.
3. The method of claim 1 , further comprising:
removing the non-volatile charge trapping dielectric stack over the first region of the semiconductor substrate;
performing a thermal oxidation to form a first gate insulator layer over the first region of the semiconductor substrate and to thermally reoxidize the blocking layer; and
performing a nitridation process to nitridize the first gate insulator layer and the blocking layer simultaneously.
4. The method of claim 1 ,
further comprising:
wherein the another MOS stack is an NMOS transistor and
implanting a second dopant species into the semiconductor substrate to form a p-well for the NMOS transistor prior to forming the non-volatile charge trapping dielectric stack over the second region of the semiconductor substrate.
5. The method of claim 4 , further comprising:
performing an n-channel implant after forming the n-well and prior to forming the nonvolatile charge trapping dielectric stack over the second region of the semiconductor substrate.
6. The method of claim 5 , further comprising:
performing a rapid thermal anneal of the substrate prior to forming the MOS gate oxide, after forming the n-well and p-well and after performing the n-channel implant, wherein the rapid thermal anneal is performed prior to forming the non-volatile charge trapping dielectric stack.
7. The method of claim 1 , wherein the substrate is single crystalline silicon, the tunneling layer comprises at least one of silicon dioxide or silicon oxy-nitride, the charge trapping layer comprises at least one of silicon nitride or silicon oxy-nitride, and the blocking layer comprises at least one of silicon dioxide or silicon oxy-nitride to form a non-volatile charge trapping dielectric stack of a SONOS memory device.
8. A method of fabricating a semiconductor structure, the method comprising:
implanting a first dopant species into a first region of a semiconductor substrate to form an n-well for a PMOS transistor;
forming a non-volatile charge trapping dielectric stack over a second region of the semiconductor substrate after forming the PMOS transistor n-well, the non-volatile charge trapping dielectric stack including a blocking layer on a charge trapping layer over a tunneling layer formed on the semiconductor substrate;
removing the non-volatile charge trapping dielectric stack over the first region of the semiconductor substrate;
performing a thermal oxidation to form a first gate insulator layer over the first region of the semiconductor substrate and to thermally reoxidize the blocking layer;
forming a gate oxide of the PMOS transistor over the first region of the semiconductor substrate after forming the first gate insulator layer;
performing a nitridation process to nitridize the first gate insulator, the gate oxide layer, and the blocking layer simultaneously; and
forming silicide over the first region of the semiconductor substrate while blocking formation of silicide over the non-volatile charge trapping dielectric stack.
9. The method of claim 8 , further comprising:
performing an implant photomask strip after implanting the first dopant species and prior to forming the non-volatile charge trapping dielectric stack.
10. The method of claim 8 , further comprising:
forming a first PMOS gate stack and another MOS gate stack over the first region of the semiconductor substrate;
forming a first sidewall spacer adjacent to the PMOS gate stack and a second sidewall spacer adjacent the another MOS gate stack;
implanting a source and drain into the first region adjacent to the first sidewall spacer;
depositing a multi-layer liner over the second sidewall spacer, the multi-layer liner including a top layer and a bottom layer;
etching the top layer selective to the bottom layer to form a disposable sidewall spacer separated from the second sidewall spacer by at least the bottom layer;
implanting a source and a drain offset from the second sidewall spacer by the disposable sidewall spacer to increase a breakdown voltage; and
removing the disposable sidewall spacer selectively to the bottom layer.
11. The method of claim 8 ,
further comprising:
wherein the another MOS stack is an NMOS transistor and
implanting a second dopant species into the semiconductor substrate to form a p-well for the NMOS transistor prior to forming the non-volatile charge trapping dielectric stack over the second region of the semiconductor substrate.
12. The method of claim 11 , further comprising:
performing an n-channel implant after forming the n-well and prior to forming the nonvolatile charge trapping dielectric stack over the second region of the semiconductor substrate.
13. The method of claim 12 , further comprising:
performing a rapid thermal anneal of the substrate prior to forming the MOS gate oxide, after forming the n-well and p-well and after performing the n-channel implant, wherein the rapid thermal anneal is performed prior to forming the non-volatile charge trapping dielectric stack.
14. The method of claim 8 , wherein the substrate is single crystalline silicon, the tunneling layer comprises at least one of silicon dioxide or silicon oxy-nitride, the charge trapping layer comprises at least one of silicon nitride or silicon oxy-nitride, and the blocking layer comprises at least one of silicon dioxide or silicon oxy-nitride to form a non-volatile charge trapping dielectric stack of a SONOS memory device.