Method of characterizing a semiconductor device and semiconductor device

1. A method of measuring a semiconductor device comprising steps of:

providing a silicon-on-insulator (SOI) substrate with at least a body-tied (BT) SOI device and a body-tied (BT) dummy device for measurement, where in the BT dummy device comprises a first conductive type source/drain heavily doped region and a dummy gate, and the dummy is not positioned on the first conductive type source/drain heavily doped region;

measuring scattering parameters (S-parameters) and tunneling currents (I gb ) of the BT SOI device and the BT dummy device, respectively;

subtracting I gb of the BT dummy device from that of the BT SOI device to obtain I gb of a floating body (FB) SOI device;

filtering characteristics of the BT dummy device out to extract S-parameters of the FB SOI device; and

analyzing the S-parameters of the FB SOI device to obtain gate-related capacitances (C gb ) of the FB SOI device.

2. The method of claim 1 , wherein the BT SOI device and the BT dummy device are simultaneously formed on the SOI substrate by same processes.

3. The method of claim 1 , wherein the SOI substrate comprises a plurality of second conductive type well.

4. The method of claim 3 , wherein the BT SOI device comprises:

a gate structure formed on the second conductive type well;

at least a first conductive type source/drain heavily doped region formed in the second conductive type well;

a second conductive type heavily doped region formed in the SOI substrate, the second conductive type heavily doped region being isolated from the first conductive type source/drain heavily doped region by the second conductive type well; and

a body electrically connected to a circuit.

5. The method of claim 4 , wherein the gate structure comprises a first part and a second part perpendicular to the first part, and the second part is formed across the second conductive type well.

6. The method of claim 5 , wherein the first part of the gate structure comprises a first conductive type region and a second conductive type region, the first conductive type region is proximal to the first conductive type source/drain heavily doped region and the second conductive type region is adjacent to the second conductive type heavily doped region.

7. The method of claim 6 , wherein the gate structure is a T-shaped gate structure.

8. The method of claim 7 , wherein the BT dummy device comprises:

a second conductive type heavily doped region; and

a body electrically connected to a circuit; wherein

the dummy gate is positioned on the second conductive type well and comprises a first conductive type region and a second conductive type region, the first conductive type region is proximal to the first conductive type source/drain heavily doped region and the second conductive type region is proximal to the second conductive type heavily doped region.

9. The method of claim 6 , wherein the gate structure is a H-shaped gate structure, and the first parts of the H-shaped gate structure are positioned parallel to each other and on opposite ends of the second part.

10. The method of claim 9 , wherein the BT dummy device comprise:

a second conductive type heavily doped region; and

a body electrically connected to a circuit; wherein

the dummy gates is a pair of dummy gates positioned parallel to each on the second conductive type well and respectively comprises a first conductive type region and a second conductive type region, the first conductive type region is proximal to the first conductive type source/drain heavily doped region and the second conductive type region is proximal to the second conductive type heavily doped region.

11. The method of claim 1 , wherein the BT SOI device and the BT dummy device are constructed in a radio frequency (RF) test key.

12. The method of claim 1 , wherein the SOI substrate is a device wafer or a monitor wafer.

13. A semiconductor device comprising:

a SOI substrate having a second conductive type well;

a first conductive type source/drain heavily doped region formed in the second conductive type well;

a second conductive type heavily doped region formed in the SOI substrate, the second conductive type heavily doped region being isolated from the first conductive type source/drain heavily doped region by the second conductive type well;

a dummy gate positioned on the first conductive type well, the dummy gate being not across the first conductive type source/drain heavily doped region; and

a body-tied (BT) body electrically connected to a circuit.

14. The semiconductor device of claim 13 , wherein the SOI substrate sequentially comprises a substrate, a buried oxide (BOX) layer and a first conductive type doped silicon layer.

15. The semiconductor device of claim 13 , wherein the dummy gate comprises a first conductive type region and a second conductive type region, the first conductive type region is proximal to the first conductive type source/drain heavily doped region and the second conductive type region is proximal to the second conductive type heavily doped region.

16. The semiconductor device of claim 13 , wherein the dummy gate comprises a pair of structures parallel to each other.

17. The semiconductor device of claim 13 , wherein the semiconductor device is constructed in a RF test key.

18. The semiconductor device of claim 13 , wherein the SOI substrate is a device wafer.

19. The semiconductor device of claim 18 , wherein the semiconductor device is formed in scribe lines of the device wafer.

20. The semiconductor device of claim 13 , wherein the SOI substrate is a monitor wafer.