IP Library › Granted Patent US 8,095,173

Granted Patent B2

US 8,095,173 · App. 12/064,199 · Granted Jan 10, 2012

Wireless communication device with physical-layer reconfigurable processing engines

Assignee: Intel Corporation

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Quick Facts

Patent No.: US 8,095,173
App. No.: 12/064,199
Granted: Jan 10, 2012
Kind: B2

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Abstract

Embodiments of a system and method for signal processing in a wireless communication device are generally described herein. Other embodiments may be described and claimed. In some embodiments, the wireless communication device comprises a first reconfigurable processing engine for configuration by a processing unit to perform a plurality of baseband processing operations on baseband samples. The processing unit may reconfigure the first reconfigurable processing engine for performing each of the plurality of baseband processing operations after completion of a prior one of the baseband processing operations. A second reconfigurable processing engine for configuration by the processing unit may perform decoding operations on output data generated by the first reconfigurable processing engine.

Claims (76)

1. A wireless communication device comprising:

a first reconfigurable processing engine for configuration by a processing unit to perform a plurality of baseband processing operations on baseband samples, the processing unit to reconfigure the first reconfigurable processing engine for performing each of the plurality of baseband processing operations after completion of a prior one of the baseband processing operations; and

a second reconfigurable processing engine for configuration by the processing unit to perform decoding operations on output data generated by the first reconfigurable processing engine;

a high-speed data path inaccessible by the processing unit and coupling the first and second reconfigurable processing engines; and

a system bus coupling the processing unit and the first and second reconfigurable processing engines for reconfiguring the first and second reconfigurable processing engines,

wherein output data generated by the first reconfigurable processing engine is provided to the second reconfigurable processing engine over the high-speed data path,

wherein the plurality of baseband processing operations comprise at least one of frequency correction operations, Fourier transform operations and demodulation operations, and

wherein the wireless communication device further comprises a sample buffer to store the baseband samples,

wherein the processing unit is configured to configure the first reconfigurable processing engine to perform frequency correction operations when a predetermined number of baseband samples are stored in the sample buffer,

wherein after the frequency corrections operations are complete, the processing unit is configured to configure the first reconfigurable processing engine to perform fast Fourier transform (FFT) operations; and

wherein after the FFT operations are complete, the processing unit is configured to configure the first reconfigurable processing engine to perform equalization, phase correction and demodulation operations concurrently.

2. The wireless communication device of claim 1 wherein the demodulation operation includes storing soft bits in an input buffer of the second reconfigurable processing engine,

wherein the first reconfigurable processing engine is configured to instruct the second reconfigurable processing engine upon completion of the demodulation operation, and the processing unit is configured to instruct the second reconfigurable processing engine to begin frame decoding operations,

wherein the second reconfigurable processing engine is configured to perform frame decoding operations on a current frame while the first reconfigurable processing engine performs operations on a next frame.

3. The wireless communication device of claim 2 wherein the first reconfigurable processing engine writes the soft bits to the input buffer and the second reconfigurable processing engine reads the soft bits from the input buffer to perform a block interleaving operation on the soft bits.

4. The wireless communication device of claim 1 wherein the FFT operations comprise a plurality of stages of FFT operations,

wherein after each stage of FFT operations, the processing unit is configured to at least partially reconfigure the first reconfigurable processing engine to perform a next stage of FFT operations until a final stage of FFT operations is performed.

5. A wireless communication device comprising:

a second reconfigurable processing engine for configuration by the processing unit to perform decoding operations on output data generated by the first reconfigurable processing engine;

a high-speed data path inaccessible by the processing unit and coupling the first and second reconfigurable processing engines; and

a system bus coupling the processing unit and the first and second reconfigurable processing engines for reconfiguring the first and second reconfigurable processing engines,

wherein output data generated by the first reconfigurable processing engine is provided to the second reconfigurable processing engine over the high-speed data path,

wherein the first and second reconfigurable processing engines each comprise memory, address generators, functional units, a reconfigurable interconnect network, and a run-time reconfigurator,

wherein the reconfiguration instructions received from the processing unit comprise instructions to change connections within the reconfigurable interconnect network and change one or more functions performed by the functional units,

wherein the instructions further include instructions to upload an address table by the address generators,

wherein the baseband samples are stored in a sample buffer,

wherein the processing unit is configured to configure the first reconfigurable processing engine to perform frequency correction operations when a predetermined number of the baseband samples are stored in the sample buffer,

6. A method for signal processing comprising:

configuring a first reconfigurable processing engine by a processing unit to perform a plurality of baseband processing operations on baseband samples, the processing unit to reconfigure the first reconfigurable processing engine for performing each of the baseband processing operations after completion of a prior one of the baseband processing operations;

configuring a second reconfigurable processing engine by the processing unit to perform decoding operations on output data generated by the first reconfigurable processing engine; and

communicating the output data over a high-speed data path coupling the first and second reconfigurable processing engines, the high-speed data path being inaccessible to the processing unit,

wherein the processing unit reconfigures the first and second reconfigurable processing engines over a system bus,

wherein the baseband processing operations comprise at least one of frequency correction operations, Fourier transform operations and demodulation operations,

wherein the wireless communication device further comprises a sample buffer to store the baseband samples,

7. The method of claim 6 wherein the baseband processing operations further comprise at least one of equalization operations and phase correction operations the demodulation operation includes storing soft bits in an input buffer of the second reconfigurable processing engine,

8. The method of claim 7 wherein the first reconfigurable processing engine writes the soft bits to the input buffer and the second reconfigurable processing engine reads the soft bits from the input buffer to perform a block interleaving operation on the soft bits.

9. The method of claim 6 wherein the FFT operations comprise a plurality of stages of FFT operations,

10. A method for signal processing comprising:

configuring a second reconfigurable processing engine by the processing unit to perform decoding operations on output data generated by the first reconfigurable processing engine; and

communicating the output data over a high-speed data path coupling the first and second reconfigurable processing engines, the high-speed data path being inaccessible to the processing unit,

wherein the processing unit reconfigures the first and second reconfigurable processing engines over a system bus,

wherein the first and second reconfigurable processing engines each comprise memory, address generators, functional units, a reconfigurable interconnect network, and a run-time reconfigurator,

wherein the method further comprises receiving the reconfiguration instructions from the processing unit to change connections within the reconfigurable interconnect network, to change one or more functions performed by the functional units, and to upload an address table by the address generators,

wherein the baseband samples are stored in a sample buffer,

11. Processing circuitry for a wireless communication device comprising:

two or more reconfigurable processing engines; and

a processing unit to perform higher-latency operations and to reconfigure the two or more reconfigurable processing engines with run-time reconfigurators and to control the two or more reconfigurable processing engines via state registers,

wherein a first of the reconfigurable processing engines performs lower-latency operations on complex baseband signals including signal detection, frequency correction and Fourier transform operations to generate soft-bit vectors, the first reconfigurable processing engine being reconfigured by the processing unit for separately performing each of the lower-latency operations, and

wherein a second of the reconfigurable processing engines is configured to perform decoding operations on the soft-bit vectors, the soft-bit vectors being received from the first reconfigurable processing engine over a high-speed data path inaccessible by the processing unit,

wherein the complex baseband signals are generated from received orthogonal frequency division multiplexed signals,

wherein the processing unit configures the second reconfigurable processing engine to perform decoding operations comprising one of Viterbi decoding operations, Turbo-decoding operations, Reed-Solomon decoding operations, or low-density-parity check decoding operations,

wherein the first and second reconfigurable processing engines each comprise memory, address generators, functional units, a reconfigurable interconnect network, and a run-time reconfigurator,

wherein the reconfiguration instructions received from the processing unit comprise instructions to change connections within the reconfigurable interconnect network and to change one or more functions performed by the functional units,

wherein the instructions further including instructions to upload an address table by the address generators,

wherein the complex baseband samples are stored in a sample buffer,

12. The processing circuitry of claim 11 wherein the FFT operations comprise a plurality of stages of FFT operations, wherein after each stage of FFT operations, the processing unit is configured to at least partially reconfigure the first reconfigurable processing engine to perform a next stage of FFT operations until a final stage of FFT operations is performed.

13. The processing circuitry of claim 11 wherein the demodulation operation includes storing soft bits in an input buffer of the second reconfigurable processing engine,

14. The processing circuitry of claim 13 wherein the first reconfigurable processing engine writes the soft bits to the input buffer and the second reconfigurable processing engine reads the soft bits from the input buffer to perform a block interleaving operation on the soft bits.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2008

From: CHAPYZHENKA, ALIAKSEI VLADIMIROVICH; LYAKH, MIKHAIL YURIEVICH; SEMENOV, OLEG BORISOVICH

To: INTEL CORPORATION

Reel/Frame 021456/0618 →

Continuity (1)

Related Publication 20080186887A1 · Aug 7, 2008