Managing cache line allocations for multiple issue processors

1. An apparatus comprising:

a cache configured as N-way associative; and

a controller circuit configured to (i) detect one of a cache hit and a cache miss in response to each of a plurality of access requests to said cache, (ii) detect a collision among said access requests, (iii) queue at least two first requests of said access requests that establish a speculative collision, said speculative collision occurring where said first requests access a given congruence class in said cache and (iv) delay a line allocation to said cache caused by a cache miss of a given one of said first requests while said given congruence class has at least N outstanding line fills in progress.

2. The apparatus according to claim 1 , further comprising a multiple issue processor configured to generate said access requests that cause said collision.

3. The apparatus according to claim 1 , wherein said controller circuit is further configured to end said delay of said line allocation when no more than said N outstanding line fills are in progress.

4. The apparatus according to claim 1 , wherein said cache is accessed in response to said cache hit of said given first request independent of a number of said outstanding line fills in progress.

5. The apparatus according to claim 1 , wherein said line allocation corresponding to said cache is performed in response to said cache miss of said given first request while said given congruence class has less than said N outstanding line fills in progress.

6. The apparatus according to claim 1 , wherein said controller circuit is further configured to queue in a particular order at least two second requests of said access requests that establish a true collision, said true collision occurring where said second requests are specified to access said cache in said particular order.

7. The apparatus according to claim 6 , wherein said particular order comprises an arrival order at said controller circuit.

8. The apparatus according to claim 1 , wherein said controller circuit is further configured to queue in a particular order at least two second requests of said access requests that establish a true collision, said true collision occurring where said second requests access a single cache line concurrently.

9. The apparatus according to claim 1 , wherein said controller circuit is further configured to (i) receive a plurality of new requests of said access requests and (ii) compare a plurality of addresses between said new requests and one or more active requests of said access requests to determine said collision.

10. The apparatus according to claim 1 , wherein said controller circuit is further configured to (i) receive a plurality of new requests of said access requests and (ii) compare a plurality of addresses among said new requests to determine said collision.

11. A method of managing line allocations, comprising the steps of:

(A) detecting a collision among a plurality of access requests to a cache using a controller circuit, said cache configured as N-way associative;

(B) queuing at least two first requests of said access requests that establish a speculative collision in a controller circuit, said speculative collision occurring where said first requests access a given congruence class in said cache; and

(C) delaying a line allocation to said cache caused by a cache miss of a given one of said first requests is delayed while said given congruence class has at least N outstanding line fills in progress.

12. The method according to claim 11 , further comprising the step of:

generating said access requests that cause said collision using a multiple issue processor.

13. The method according to claim 11 , further comprising the step of:

ending said delay of said line allocation when no more than said N outstanding line fills are in progress.

14. The method according to claim 11 , further comprising the step of:

accessing said cache in response to said cache hit of said given first request independent of a number of said outstanding line fills in progress.

15. The method according to claim 11 , further comprising the step of:

performing said line allocation to said cache in response to said cache miss of said given first request while said given congruence class has less than said N outstanding line fills in progress.

16. The method according to claim 11 , further comprising the step of:

queuing in a particular order at least two second requests of said access requests that establish a true collision, said true collision occurring where said second requests are specified to access said cache in said particular order.

17. The method according to claim 16 , wherein said particular order comprises an arrival order at said controller circuit.

18. The method according to claim 11 , further comprising the step of:

queuing in a particular order at least two second requests of said access requests that establish a true collision, said true collision occurring where said second requests access a single cache line concurrently.

19. The method according to claim 11 , further comprising the steps of:

receiving a plurality of new requests of said access requests; and

comparing a plurality of addresses between said new requests and one or more active requests of said access requests to determine said collision.

20. An apparatus comprising:

means for caching configured as N-way associative; and

means for controlling configured to (i) detect one of a cache hit and a cache miss in response to each of a plurality of access requests to said means for caching, (ii) detect a collision among said access requests, (iii) queue at least two first requests of said access requests that establish a speculative collision, said speculative collision occurring where said first requests access a given congruence class in said means for caching and (iv) delay a line allocation to said means for caching caused by a cache miss of a given one of said first requests while said given congruence class has at least N outstanding line fills in progress.