One phase logic
Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.
1. A method comprising:
identifying at least one idle portion of an asynchronous linear pipeline circuit that includes a portion of multi-phase logic and acknowledge circuits; and
converting the identified at least one idle portion of the asynchronous linear pipeline circuit to a one-phase pipeline circuit.
2. The method of claim 1 , wherein identifying the at least one idle portion comprises identifying a portion that is empty.
3. The method of claim 1 , wherein forming the asynchronous linear pipeline circuit comprises forming at least one of a four-phase or a two-phase pipeline circuit.
4. The method of claim 1 , wherein the converting to the one-phase pipeline circuit further comprises disregarding acknowledge signals from acknowledge circuits corresponding to the idle portion.
5. The method of claim 1 , further comprising implementing the one-phase pipeline in a field programmable gate array.
6. The method of claim 1 , wherein the one-phase pipeline circuit further comprises a plurality of data signals on a plurality of wires, and wherein the converting further comprises reducing delay mismatches corresponding to the data signals.
7. The method of claim 1 , further comprising combining a first set of data signals from a first one-phase pipeline circuit with a second set of data signals from a second one-phase pipeline circuit.
8. The method of claim 7 , further comprising adding a delay to one of the first one-phase pipeline circuits or the second one-phase pipeline circuit to substantially match pipeline delays associated with each of the first and second one-phase pipeline circuits.
9. The method of claim 7 , further comprising adding an acknowledge circuit to one of the first one-phase pipeline circuits or the second one-phase pipeline circuit to accommodate a potential stall condition in the first or second one-phase pipeline circuit.
10. The method of claim 7 , further comprising:
determining that a first data rate associated with the first one-phase pipeline circuit is higher than a second data rate associated with the second one-phase pipeline circuit; and
based on the determination, decreasing the first data rate to match the second data rate.
11. The method of claim 7 , further comprising:
determining that a first data rate associated with the first one-phase pipeline circuit is higher than a second data rate associated with the second one-phase pipeline circuit; and
based on the determination introducing a dummy communication circuit between the first one-phase pipeline circuit and the second one-phase pipeline circuit to balance a delay.
12. A circuit comprising:
a plurality of one-phase pipeline circuits that operate to disregard acknowledge signals in idle portions of a plurality of asynchronous linear pipeline circuits; and
a plurality of connection blocks to provide a set of connections between a selected number of the plurality of asynchronous linear pipeline circuits and the plurality of one-phase pipeline circuits.
13. The circuit of claim 12 , wherein a connection between a first one-phase pipeline circuit and a second one-phase pipeline circuit is formed by a dummy circuit disposed between the first one-phase pipeline circuit and the second one-phase pipeline circuit.
14. The circuit of claim 12 , wherein a connection between a first one-phase pipeline circuit and a second one-phase pipeline circuit is formed by a delay element in the first one-phase pipeline circuit.
15. The circuit of claim 12 , wherein a connection between a first one-phase pipeline circuit and a second one-phase pipeline circuit is formed by an acknowledge circuit in the first one-phase pipeline circuit.
16. The circuit of claim 12 , wherein the asynchronous linear pipeline circuits and the one-phase pipeline circuits are implemented in a field programmable gate array.
17. A system comprising:
memory;
one or more processors coupled to the memory, the one or more processors to implement one or more modules including;
an identification module to identify at least one idle portion of an asynchronous linear pipeline circuit that includes a portion of multi-phase logic and acknowledge circuits; and
a conversion module to convert the identified at least one idle portion of the asynchronous linear pipeline circuit to a one-phase pipeline circuit.
18. The system of claim 17 , wherein the conversion module is to disregard acknowledge signals from acknowledge circuits corresponding to the idle portion.
19. The system of claim 17 , wherein the one-phase pipeline circuit further comprises a plurality of data signals on a plurality of wires, and wherein the conversion module is to reduce delay mismatches corresponding to the data signals.
20. A machine-readable storage medium containing instructions that when executed by a machine, cause the machine to perform a method comprising:
identifying at least one idle portion of an asynchronous linear pipeline circuit that includes a portion of multi-phase logic and acknowledge circuits; and
converting the identified at least one idle portion of the asynchronous linear pipeline circuit to a one-phase pipeline circuit.