IP Library Granted Patent US 8,110,431
Granted Patent B2
US 8,110,431 · App. 12/793,363 · Granted Feb 7, 2012

Ion implanted selective emitter solar cells with in situ surface passivation

Assignee: Suniva, Inc.
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Quick Facts
Patent No.
US 8,110,431
App. No.
12/793,363
Granted
Feb 7, 2012
Kind
B2
Abstract

Solar cells and methods for their manufacture are disclosed. An example method may include providing a p-type doped silicon substrate and introducing n-type dopant to a first and second region of the front surface of the substrate by ion implantation so that the second region is more heavily doped than the first region. The substrate may be subjected to a single high-temperature anneal cycle to activate the dopant, drive the dopant into the substrate, produce a p-n junction, and form a selective emitter. Oxygen may be introduced during the single anneal cycle to form in situ front and back passivating oxide layers. Fire-through of front and back contacts as well as metallization with contact connections may be performed in a single co-firing operation. Associated solar cells are also provided.

Claims (25)

1. A method for manufacturing a selective emitter solar cell comprising:

providing a substrate comprising a p-type base layer;

introducing dopant to at least a first region of the front surface of the p-type base layer by ion implantation;

introducing dopant to at least a second region of the front surface of the p-type base layer by ion implantation, wherein the second region is more heavily doped than the first region, and wherein the dopant introduced to the first and second regions is of n-type conductivity;

annealing the substrate, wherein annealing comprises heating the substrate in a furnace to a temperature to:

anneal the implant damage;

activate dopant from the first and second regions; and

drive the dopant from the first and second regions deeper into the substrate, thereby forming a selective emitter layer on the front surface of the p-type base layer;

introducing oxygen into the furnace during the annealing step to:

form a passivating oxide layer on at least the front surface of the selective emitter layer;

depositing an amorphous silicon nitride layer on the front surface of the passivating oxide layer thereby forming an antireflection layer;

screen-printing one or more front contacts on the amorphous silicon nitride layer in alignment with the second region of the front surface of the p-type base layer;

screen-printing one or more aluminum back contacts on the back surface of the p-type base layer;

co-firing the one or more front and back contacts to provide electrical connections to the solar cell; and

forming an aluminum-doped p + silicon layer by liquid phase epitaxial regrowth at the interface of the back surface of the p-type base layer and the back contacts during the co-firing of the front and back contacts, wherein the back contacts provide an electrical connection to the aluminum-doped p + silicon layer.

2. The method of claim 1 wherein the substrate is a monocrystalline, Czochralski silicon substrate.

3. The method of claim 1 wherein the dopant comprises phosphorus.

4. The method of claim 1 wherein introducing dopant to at least the first region comprises uniformly introducing dopant to the first and second regions of the front surface of the p-type base layer, and wherein introducing dopant to at least the second region comprises introducing additional dopant through a mask to at least the second region of the front surface of the p-type base layer.

5. The method of claim 1 wherein annealing the substrate does not create an electrical shunt path between the front surface of the selective emitter layer and the back surface of the p-type base layer, and wherein annealing the substrate does not form a phosphosilicate glass.

6. The method of claim 1 wherein the front contacts are formed using a metal paste comprising frit such that the frit allows the one or more front contacts to penetrate the amorphous silicon nitride layer and the passivating oxide layer to provide an electrical connection to the selective emitter layer.

7. The method of claim 1 wherein introducing dopant to the first and second regions occurs during a single implantation step.

8. The method of claim 1 wherein the substrate is a crystalline silicon substrate.

9. The method of claim 8 wherein the substrate is a multicrystalline silicon substrate.

10. The method of claim 1 wherein introducing dopant to at least the first region comprises uniformly introducing dopant to the first and second regions of the front surface of the p-type base layer.

11. The method of claim 1 wherein introducing dopant to at least the second region comprises introducing additional dopant through a mask to at least the second region of the front surface of the p-type base layer.

Assignments (3)
SECURITY INTEREST Recorded Dec 17, 2015
From: SUNIVA, INC.
To: SQN ASSET SERVICING, LLC
Reel/Frame 037316/0228 →
PATENT AND TRADEMARK SECURITY AGREEMENT Recorded Jun 14, 2012
From: SUNIVA, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 028380/0595 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2010
From: YELUNDUR, VIJAY; DAMIANI, BEN; CHANDRASEKARAN, VINODH; DAVIS, HUBERT PRESTON; ROHATGI, AJEET
To: SUNIVA, INC.
Reel/Frame 024757/0673 →
Continuity (1)
Related Publication 20110139230A1 · Jun 16, 2011