Method of fabricating semiconductor device isolation structure
View Patent ↗A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
1. A semiconductor device, comprising a semiconductor substrate comprising an isolation structure, the isolation structure exhibiting a reentrant profile defining a reentrant tangent line deviating at least about 5° from a line normal to the semiconductor substrate, wherein the isolation structure has a first width overlying a larger second width, wherein the isolation structure is separated from the semiconductor substrate by a diffusive boundary and wherein the isolation structure has a top surface that is planar and is co-planar with the semiconductor substrate.
2. The semiconductor device of claim 1 , wherein the at least one isolation structure comprises carbon.
3. The semiconductor device of claim 1 , wherein the at least one isolation structure comprises nitrogen.
4. The semiconductor device of claim 1 , wherein the at least one isolation structure comprises oxygen.
5. The semiconductor device of claim 1 , wherein the reentrant tangent line deviates about 30° from a line normal to the substrate.
6. The semiconductor device of claim 5 , wherein a lateral dimension of the isolation region is greatest about one-half way between its upper and lower boundary.
7. A substrate for fabricating semiconductor devices, comprising:
an active area; and
a first isolation region directly adjacent to the active area, wherein the first isolation region has a first width and a second width larger than the first width, the second width being located further into the substrate than the first width, wherein the first isolation region has a reentrant profile defining a first reentrant tangent line deviating at least about 5° from a line normal to the substrate, and wherein the first isolation region is an insulator and is separated from the semiconductor substrate by a diffusive boundary.
8. The substrate of claim 7 , wherein the first reentrant tangent line deviates at least about 30° from a line normal to the substrate.
9. The substrate of claim 8 , further comprising a second isolation region directly adjacent to the active area and opposite the first isolation region.
10. The substrate of claim 9 , wherein the first isolation region and the second isolation region overlap.
11. The substrate of claim 8 , wherein the first isolation region exhibits a substantially symmetrical profile with respect to the line normal to the substrate.
12. A semiconductor device, comprising:
a substrate;
an active area formed on the substrate;
a first isolation region exhibiting a reentrant profile adjacent a first side of the active area, wherein the first isolation region has a first width at a first depth and a second width at a second depth, wherein the first depth is closer to a top surface of the first isolation region than the second depth, and the first width is smaller than the second width; and
a second isolation region exhibiting a reentrant profile adjacent a second side of the active area, wherein the first isolation region and the second isolation region overlap under the active area.
13. The semiconductor device of claim 12 , wherein the isolation regions are integrally-formed with the substrate.
14. The semiconductor device of claim 12 , wherein a reentrant tangent line on the active-area side of the first isolation region is at an angle about 30° from the normal line.
15. The semiconductor device of claim 12 , wherein the first isolation region and the second isolation region overlap region is disposed approximately under the center of the active area.
16. The semiconductor device of claim 12 , wherein the isolation regions are formed of silicon dioxide.
17. The semiconductor device of claim 12 , wherein the isolation regions are formed of silicon nitride.
18. The semiconductor region of claim 12 , further comprising an active component formed in the active area.
19. The semiconductor device of claim 18 , wherein the active component is a transistor.