IP Library Granted Patent US 8,111,491
Granted Patent B2
US 8,111,491 · App. 12/801,675 · Granted Feb 7, 2012

Overvoltage protection circuit

Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,111,491
App. No.
12/801,675
Granted
Feb 7, 2012
Kind
B2
Abstract

An overvoltage protection circuit includes an output transistor coupled between a power supply and an output terminal, the output terminal including a terminal for being coupled to a load and a dynamic clamping circuit and a clamp selection transistor coupled in series between the power supply terminal and a control terminal of the output transistor. The clamp selection transistor is coupled between the dynamic clamping circuit and a control terminal of the output transistor. In addition, the clamp selector transistor includes an N-channel type transistor, a control terminal of the N-channel type transistor being coupled to a ground potential.

Claims (16)

1. An overvoltage protection circuit, comprising:

an output transistor coupled between a power supply and an output terminal, the output terminal comprising a terminal for being coupled to a load; and

a dynamic clamping circuit and a clamp selection transistor coupled in series between the power supply and a gate terminal of the output transistor,

wherein the clamp selection transistor is coupled between the dynamic clamping circuit and the gate terminal of the output transistor, the clamp selection transistor comprising an N-channel type transistor, a gate terminal of the N-channel type transistor being fixed to a ground potential, a substrate terminal being coupled to the output terminal.

2. The overvoltage protection circuit according to claim 1 , wherein the clamp selection transistor comprises a MOS transistor.

3. The overvoltage protection circuit according to claim 2 , wherein a substrate terminal of the clamp selection transistor is coupled to the output terminal.

4. The overvoltage protection circuit according to claim 1 , further comprising a gate charge discharging circuit coupled between the gate terminal of the output transistor and the output terminal,

wherein the output transistor is controlled by a first control signal, and

wherein the gate charge discharging circuit is controlled by a second control signal which comprises an inverted signal of the first control signal.

5. The overvoltage protection circuit according to claim 4 , further comprising a resistance coupled between the gate terminal of the output transistor and the gate charge discharging circuit.

6. The overvoltage protection circuit according to claim 5 , wherein the first control signal is inputted to the gate terminal of the output transistor via the resistance.

7. The overvoltage protection circuit according to claim 1 , wherein the dynamic clamping circuit comprises a diode.

8. The overvoltage protection circuit according to claim 7 , wherein the diode comprises a zener diode.

9. The overvoltage protection circuit according to claim 1 , wherein the output transistor and the dynamic clamping circuit are formed in a single chip.

10. The overvoltage protection circuit according to claim 1 , wherein the output transistor comprises an N-channel type transistor.

11. The overvoltage protection circuit according to claim 1 , wherein the output transistor comprises an N-channel type MOS transistor.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Oct 26, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025191/0916 →
Priority Claims (1)
JP 2005-205330 · Jul 14, 2005 · national
Continuity (2)
Continuation 11483757 · Jul 11, 2006
Related Publication 20100259860A1 · Oct 14, 2010