Shared contact structure, semiconductor device and method of fabricating the semiconductor device
A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The source/drain regions may be formed within the active region adjacent the first sidewall, and provided on the opposite side of the second sidewall. A corner protection pattern may be formed adjacent the source/drain regions and the insulating spacer, and covered by an inter-layer dielectric. A shared contact plug may be formed through the inter-layer dielectric, to be in contact with the gate electrode, corner protection pattern and source/drain regions.
1. A method of fabricating a semiconductor device, comprising:
forming a gate pattern having first and second sidewalls on either side of the gate pattern facing each other on a substrate;
forming a lightly doped drain region adjacent the first sidewall and disposed on an opposite side of the second sidewall within the substrate;
forming an insulating spacer covering the first sidewall;
forming a highly doped drain region adjacent to the first sidewall and disposed on an opposite side of the second sidewall within the substrate;
forming a corner protection pattern adjacent the highly doped drain region and the insulating spacer and contacting a sidewall of the insulating spacer;
after forming the highly doped drain region, forming an etch stop layer to cover the gate pattern, the insulating spacer, the corner protection pattern, and the highly doped drain region;
forming an inter-layer dielectric on the substrate; and
forming a contact hole penetrating a portion of the inter-layer dielectric, the etch stop layer, the corner protection pattern, and the insulating spacer,
wherein the contact hole exposes a side surface of the corner protection pattern on the first sidewall, and
wherein the etch stop layer remains except on a portion of the contact hole, and wherein the highly doped drain region is self-aligned outside of the insulating spacer.
2. The method according to claim 1 , further comprising:
forming an isolation layer defining an active region within the substrate prior to forming the gate pattern.
3. The method according to claim 1 , wherein the corner protection pattern is formed of a nitride layer.
4. The method according to claim 1 , further comprising:
forming a contact plug filled in the contact hole, wherein the interlayer dielectric and contact plug are formed after the corner protection pattern.
5. The method according to claim 4 , further comprising:
forming a gate metal silicide layer on a top surface of the gate pattern; and
forming a source/drain metal silicide layer on a top surface of the highly doped drain region, where the gate metal silicide layer and source/drain metal silicide layer are formed prior to forming the corner protection pattern.
6. The method according to claim 5 , wherein forming the corner protection pattern comprises:
forming a nitride layer on the substrate having the insulating spacer and the source/drain metal silicide layer; and
anisotropically etching the nitride layer until the source/drain metal silicide layer is exposed.
7. The method according to claim 5 , wherein the contact plug is in contact with the corner protection pattern and the source/drain metal silicide layer.
8. The method according to claim 5 , wherein the contact plug is in contact with the gate metal silicide layer, corner protection pattern and source/drain metal silicide layer.
9. The method according to claim 5 , wherein the corner protection pattern contacts with a top surface of the source/drain metal silicide layer, and wherein the corner protection pattern remains except on a sidewall of the source/drain metal silicide layer.
10. A method of forming a semiconductor device, comprising:
forming a gate pattern having first and second sidewalls on either side thereof on a substrate;
covering the first sidewall with an insulating spacer;
forming a source/drain region below the insulating spacer and adjacent the first sidewall but opposite the side of the gate pattern having the second sidewall;
forming a corner protection pattern adjacent the source/drain region and the insulating spacer;
after forming the source/drain region, forming an etch stop layer to cover the gate pattern, the insulating spacer, the corner protection pattern, and the source/drain region;
forming an inter-layer dielectric on the substrate; and
forming a contact hole penetrating a portion of the inter-layer dielectric, the etch stop layer, the corner protection pattern, and the insulating spacer,
wherein the contact hole exposes a side surface of the corner protection pattern on the first sidewall, and
wherein the etch stop layer remains except on a portion of the formed contact hole, and wherein the source/drain region is self-aligned outside of the insulating spacer.