Integrated circuit device with a semiconductor body and method for the production of an integrated circuit device

1. A method of producing an integrated circuit device, comprising:

forming a trench structure having trench walls in a semiconductor body for a cell field and an edge trench in an edge region;

forming mesa structures for drift zones of a first conduction type in the cell field;

applying an oxide layer forming a field plate isolation on the trench walls and a field oxide in the edge region of a front side of the semiconductor body;

introducing field plate material into the trench structure and the edge trench;

exposing upper regions of the trench walls in the cell field;

applying a gate oxide to the exposed upper region of the trench walls;

introducing a gate electrode material into the upper regions of the trench structure; and

ion implantation of doping materials for a complementary conduction type accompanied by the formation of body zones on the mesa structures in the cell field and by the formation of an edge zone of a complementary conduction type with doping materials of the body zone below the field oxide in the edge region within and outside the edge trench.

2. The method of claim 1 , wherein the trench structure for the cell field and the edge is produced by means of a single etching step.

3. The method of claim 1 , wherein an insulating layer which forms a field plate insulation on the trench walls and an insulator in the edge regions of the front side of the semiconductor body is applied by a thermal oxidation of a silicon semiconductor material and/or by means of the deposition of an insulator material.

4. The method of claim 1 , wherein the field plate material is introduced into the trench structure and the edge trench by introducing a conductive material or a metal alloy into the trench structure and the edge trench.

5. The method of claim 1 , wherein the field plate material is introduced into the trench structure and the edge trench by means of polysilicon deposition.

6. The method of claim 1 , wherein a continuous annular channel stopper is implemented at the lateral end of the edge zone prior to the introduction of the doping materials of the body zones, said channel stopper acting as a masking limit for an ion implantation of the edge zone of the complementary conduction type.

7. The method of claim 1 , wherein the upper region of the trench walls in the cell field is exposed by a selective oxide layer wet etching process following the covering of the field oxide to be protected in the edge region.

8. The method of claim 1 , wherein the upper region of the trench walls in the cell field is exposed by a selective oxide layer dry etching process following the covering of the field oxide to be protected in the edge region.

9. The method of claim 1 , wherein a gate oxide is applied to the exposed upper region of the trench walls by a thermal oxidation of the exposed semiconductor material.

10. The method of claim 1 , wherein gate electrode material is introduced into the upper region of the trench structure by depositing a conductive material in the upper region of the trench structure.

11. The method of claim 1 , wherein, for the ion implantation of doping materials for a complementary conduction type accompanied by the formation of body zones on the mesa structures in the cell field and by the formation of an edge zone of a complementary conduction type with a body zone doping below the field oxide in the edge region, boron ions are implanted from the front side of the semiconductor body.

12. The method of claim 1 , wherein for the ion implantation of doping materials for a complementary conduction type, a first implantation step is first carried out for the formation of body zones on the mesa structures in the cell field, followed by a second implantation step for the formation of an edge zone of a complementary conduction type with a body zone doping below the field oxide in the edge region.

13. The method of claim 1 , wherein the concentration of doping material of the edge zone of the complementary conduction type is matched to the relevant breakdown voltage class of a power semiconductor device.

14. The method of claim 1 , wherein the following is carried out on a semiconductor wafer to complete the semiconductor device:

introduction of source zones with a higher concentration of doping material than the drift zones into regions of the body zones:

application of a further structured insulating layer;

introduction of contact holes for vias into the cell field for bonding the source zones, body zones and field plates;

introduction of contact holes for vias into the cell field for bonding the trench gate structure;

application of a structured metallization layer while jointly bonding the source zones, body zones and field plates, accompanied by the formation of a source connection electrode, the bonding of the trench gate structure and the formation of a gate connection electrode;

division of the semiconductor wafer into semiconductor chips; and

installation of at least one semiconductor chip into a housing to produce a semiconductor device.