Manufacturing method of semiconductor device, evaluation method of semiconductor device, and semiconductor device
View Patent ↗A semiconductor element formed over the same substrate as a TFT, includes a semiconductor film having an impurity region; an insulating film formed over the semiconductor film; an electrode divided into a plurality of parts over the insulating film by spacing a distance a in a first direction (channel width direction); an insulator with a width b formed to be in contact with a side wall of the electrodes and an insulator formed in a region between the electrodes divided into a plurality of parts; a silicide layer formed over part of the surface of the impurity region; and characteristics of the TFT are evaluated by measuring resistance of the semiconductor film of the semiconductor element.
1. A semiconductor device comprising:
a first insulating film over a substrate;
an island-shaped semiconductor film having an impurity region over the first insulating film, the impurity region comprising:
a first region over the first insulating film; and
a second region over the first region;
a second insulating film, which is over the island-shaped semiconductor film, formed so as to expose a portion of the impurity region;
a first electrode and a second electrode separated in a direction over the second insulating film, wherein the first electrode and the second electrode overlap the island-shaped semiconductor film so that a first channel formation region and a second channel formation region are formed in the impurity region, and wherein the first electrode and the second electrode are aligned along a channel width direction of the first channel formation region;
a first insulator on a first side face of each of the first electrode and the second electrode, and a second insulator in a region between a second side face of the first electrode and a second side face of the second electrode, and
a resistive element formed in the impurity region between the first channel formation region and the second channel formation region,
wherein a metal silicide is formed in the second region.
2. A semiconductor device according to claim 1 , wherein the semiconductor device includes an element for evaluation having the first electrode and the second electrode.
3. A semiconductor device according to claim 1 , wherein the resistive element comprises the first electrode and the second electrode.
4. A semiconductor device according to claim 1 , wherein the impurity region is formed by adding an impurity element by using the first electrode and the second electrode as masks.
5. A semiconductor device according to claim 1 ,
wherein the first electrode and the second electrode are separated by a distance “a”,
wherein the first insulator has a width “b”, and
wherein the distance “a” between the first electrode and the second electrode and the width “b” of the first insulator satisfy a relation of a<2b.
6. A semiconductor device according to claim 1 , wherein the first insulator is a sidewall.
7. A semiconductor device according to claim 1 , wherein the metal silicide includes an element selected from the group consisting of nickel, titanium, cobalt, and platinum.
8. The semiconductor device according to claim 1 is a test element group.
9. The semiconductor device according to claim 1 , wherein a metal silicide is not formed in the first region.
10. A semiconductor device comprising:
a first insulating film over a substrate;
an island-shaped semiconductor film having an impurity region over the first insulating film, the impurity region comprising:
a first region over the first insulating film; and
a second region over the first region;
a second insulating film, which is over the island-shaped semiconductor film, formed so as to expose a portion of the impurity region;
a first electrode and a second electrode separated in a direction over the second insulating film, wherein the first electrode and the second electrode overlap the island-shaped semiconductor film so that a first channel formation region and a second channel formation region are formed in the impurity region, and wherein the first electrode and the second electrode are aligned along a channel width direction of the first channel formation region;
a first insulator on a first side face of each of the first electrode and the second electrode, and a second insulator in a region between a second side face of the first electrode and a second side face of the second electrode;
a resistive element formed in the impurity region between the first channel formation region and the second channel formation region;
an interlayer insulating film over the second region, the first electrode and the second electrode; and
a conductive layer which is in contact with the second region through a contact hole in the interlayer insulating film
wherein a metal silicide is formed in the second region.
11. A semiconductor device according to claim 10 , wherein the semiconductor device includes an element for evaluation having the first electrode and the second electrode.
12. A semiconductor device according to claim 10 , wherein the resistive element comprises the first electrode and the second electrode.
13. A semiconductor device according to claim 10 , wherein the impurity region is formed by adding an impurity element by using the first electrode and the second electrode as masks.
14. A semiconductor device according to claim 10 ,
wherein the first electrode and the second electrode are separated by a distance “a”,
wherein the first insulator has a width “b”, and
wherein the distance “a” between the first electrode and the second electrode and the width “b” of the first insulator satisfy a relation of a<2b.
15. A semiconductor device according to claim 10 , wherein the first insulator is a sidewall.
16. A semiconductor device according to claim 10 , wherein the metal silicide includes an element selected from the group consisting of nickel, titanium, cobalt, and platinum.
17. The semiconductor device according to claim 10 is a test element group.
18. The semiconductor device according to claim 10 , wherein a metal silicide is not formed in the first region.