Method of manufacturing high-integrated semiconductor device and semiconductor device manufactured using the same
A semiconductor device comprises a plurality of vertical transistors each comprising barrier metal layers corresponding to source/drain regions in which a conduction region is formed under a channel region having a pillar form, and a bit line comprising a metal layer to connect the plurality of vertical transistors.
1. A method for manufacturing a semiconductor device, comprising:
etching a semiconductor substrate in a first direction to form a silicon line pattern;
depositing a first metal layer in a space defined by the silicon line pattern;
forming a plurality of pillars by etching the silicon line patterns and the first metal layer in a second direction crossing the first direction, the pillars being connected by the first metal layer;
etching a lower portion of each pillar; and
forming a second metal layer in the etched lower portion of each pillar, the second metal layer contacting the first metal layer.
2. The method according to claim 1 , wherein the second metal layer is configured to connect the first metal layer in the second direction.
3. The method according to claim 1 , further comprising:
forming a gate oxide layer and a gate electrode around each pillar; and
forming a conductive layer to connect the gate electrode of each pillar in the first direction.
4. The method according to claim 1 , wherein etching the lower portion of each pillar involves forming concave regions by isotropically etching the lower portion of each pillar, the method further comprising:
removing part of the second metal layer by performing an etchback process, the second metal layer remaining in the concave regions; and
sintering the second metal layer remaining in the concave regions using a silylation process.
5. The method according to claim 1 , wherein etching the lower portion of each pillar involves forming concave regions by isotropically etching the lower portion of each pillar, the method further comprising:
removing part of the second metal layer by performing a wet etch process, the second metal layer remaining in the concave regions; and
sintering the second metal layer remaining in the concave regions using a silylation process.