Method and apparatus for accessing a non-volatile memory array comprising unidirectional current flowing multiplexers
A non-volatile memory (NVM) having an array of memory cells and a unidirectional multiplexer (UMUX), the UMUX may be comprised of two or more address line ports adapted to receive addressing signals corresponding with elements in the memory array, and a set of switching transistors adapted to switch a supply voltage in accordance with the addressing signal such that current only flows into the array.
1. A non-volatile memory (NVM) memory device comprising: an array of memory cells; a unidirectional multiplexer (UMUX), the UMUX comprising two or more address line ports adapted to receive addressing signals corresponding with elements in the memory array, and a set of switching transistors adapted to switch a supply voltage in accordance with the addressing signal such that current only flows into the array; and a multiplexer (Y-MUX), the Y-MUX comprising two or more address line ports adapted to receive addressing signals corresponding with the elements in the memory array, a set of switching transistors adapted to switch a supply voltage in accordance with the addressing signal such that current flows into the array, and a set of switching transistors adapted to switch an operating current in accordance with the addressing signal such that current flows out of the array.
2. The NVM device of claim 1 wherein the elements comprise at least one global source bit line (GSBL) adapted to carry the current flowing into the array.
3. The NVM device of claim 2 wherein the GSBL is connected to at least one local source bit line (LSBL).
4. The NVM device of claim 1 further comprising a second UMUX, the second UMUX comprising two or more address line ports adapted to receive addressing signals corresponding with elements in the memory array, and a set of switching transistors adapted to switch an operating current in accordance with the addressing signal such that current flows out of the array.
5. The NVM device of claim 4 wherein the elements comprise at least one global drain bit line (GDBL) adapted to carry the operating current flowing out of the array.